3D DRAM Capacitor Structure With Double-Sided Through-Hole Electrodes
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Solution Overview
Problem
As semiconductor memory sizes miniaturize, it becomes increasingly difficult to maintain or increase capacitance in Dynamic Random Access Memory (DRAM) capacitors, as traditional methods to enhance capacitance, such as increasing surface area or decreasing dielectric thickness, are limited by manufacturing constraints.
Innovation Solution
The proposed solution involves forming capacitance holes with multiple isolated through holes and a double-sided capacitor structure, where the lower electrode covers the sidewalls and bottom of these holes, and a sacrificial material layer is removed to expose the electrode surfaces, allowing for a larger surface area and increased capacitance through the formation of a double-sided capacitance structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the surface area of the capacitor is increased to maintain or increase capacitance, then the capacitance is improved, but the device size increases which contradicts the miniaturization trend
Solution Approach 1:
The patent transitions from a planar capacitor structure to a three-dimensional structure by forming capacitance holes that extend vertically through multiple layers. The lower electrode covers not only the bottom but also the sidewalls of these holes, creating a vertically extended electrode surface. This dimensional transition allows the capacitor to achieve larger effective surface area for charge storage without increasing the horizontal footprint, thereby maintaining capacitance while enabling device miniaturization.
Solution Approach 2:
The patent implements a nested structure where the lower electrode is formed within and around the capacitance holes, with the dielectric layer and upper electrode nested above. The sidewall coverage creates a nested configuration where the electrode wraps around the hole structure, effectively utilizing vertical space and creating multiple surfaces for charge storage within a compact volume.
2Quantity of substance
If the dielectric material thickness is decreased to increase capacitance, then the capacitance is improved, but the manufacturing precision requirements increase
Solution Approach 1:
Instead of relying solely on reducing dielectric thickness to increase capacitance, the patent utilizes the vertical dimension by forming deep capacitance holes and extending electrodes along the sidewalls. This approach distributes the capacitance enhancement across a larger vertical extent rather than compressing the dielectric layer, thereby achieving higher capacitance without excessively thin dielectric layers that would demand extreme manufacturing precision.
3Quantity of substance
If a double-sided capacitor structure is formed to increase relative electrode area, then the capacitance is improved, but the device complexity increases
Solution Approach 1:
The patent segments the capacitor structure into distinct functional regions: capacitance holes formed through the substrate, lower electrodes covering the hole bottoms and sidewalls, dielectric layers filling the holes, and upper electrodes on top. This segmentation allows each component to be formed using specialized processes optimized for its function, managing the overall complexity by breaking down the double-sided structure into manageable segments that can be manufactured separately and assembled.
Solution Approach 2:
The patent introduces a sacrificial material layer as an intermediary during the manufacturing process. This sacrificial layer is deposited, patterned, and etched to define the capacitance hole structures, and is subsequently removed to create the final double-sided capacitor geometry. The intermediary sacrificial material simplifies the formation of complex sidewall-covered electrode structures by providing a temporary framework that guides the self-aligned formation of the lower electrodes.
Data Source
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AI summary
The present application relates to a capacitor structure and a method for manufacturing the same, and a memory using the capacitor structure. The method includes the following operations: a substrate is provided (S110); a stacked structure is formed on the substrate, the stacked structure including at least two support material layers arranged at an interval and a sacrificial material layer located between adjacent support material layers (S 120); capacitance holes is formed in the stacked structure, each of the capacitance holes including at least three through holes arranged in isolation (S 130); a lower electrode is formed, the lower electrode at least covering a side wall and a bottom of each through hole (S 140); the sacrificial material layer is removed, and a capacitance dielectric layer is formed on a surface of the lower electrode (S 150); and an upper electrode is formed on a surface of the capacitance dielectric layer (S160).