3D DRAM Cell Integration Without High-Aspect-Ratio Capacitors
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Solution Overview
Problem
The challenge of reducing the size of DRAM while maintaining high-density development is exacerbated by the high aspect ratio of the capacitor, making it difficult to achieve compact electronic devices.
Innovation Solution
A DRAM design incorporating two transistors, where one serves as a capacitor, eliminating the need for a high dielectric constant capacitor and allowing operation without a select transistor, and connecting each transistor to a conductive line to eliminate the floating body effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high dielectric constant capacitor is used in conventional 1T1C DRAM, then the capacitor can store charge effectively, but the aspect ratio of the capacitor becomes high, making size reduction difficult
Solution Approach 1:
The patent merges the capacitor function with one of the transistors by using the transistor's gate electrode as the capacitor's plate. This integration eliminates the need for a separate capacitor structure, thereby reducing the overall aspect ratio while maintaining charge storage capability through the transistor's inherent capacitance.
Solution Approach 2:
The transistor structure is designed to serve dual functions: as a switching element and as a capacitor. The gate electrode performs both the switching control function and the charge storage function, making the component universal and eliminating the need for dedicated high-aspect-ratio capacitor structures.
2Ease of operation
If a select transistor is used to operate memory cells in stacked 3D DRAM, then the memory cells can be selectively accessed, but the device complexity increases
Solution Approach 1:
The patent segments the control functions by using separate word lines and bit lines to address different memory cells in the stacked structure. Each memory cell is accessed through independent conductive lines that can be selectively activated, eliminating the need for additional select transistors within each cell while maintaining selective access capability.
Solution Approach 2:
The patent leverages the vertical stacking dimension to achieve memory cell selection. By controlling different word lines at different vertical levels through separate conductive lines, the system can selectively access memory cells in the third dimension without requiring additional transistors, thereby reducing device complexity.
3Device complexity
If transistors are not electrically connected to conductive lines, then the structure can be simpler, but the floating body effect occurs, degrading device performance
Solution Approach 1:
The patent introduces conductive lines as intermediary elements that electrically connect the transistor gates to external control circuits. These conductive lines serve as mediators that prevent the floating body effect by providing a defined electrical path, thereby improving device reliability without significantly increasing structural complexity.
Data Source
AI summary
A DRAM is provided. In the DRAM, on a substrate, first and second channel layers are separated in a first direction. A storage node is disposed between the first and second channel layers. A bit line is disposed at one side of the first channel layer away from the storage node. A word line and a first conductive are respectively disposed at opposite sides of the first channel layer in a second direction. A first dielectric layer is disposed between the word line and the first channel layer. A second dielectric layer is disposed between the storage node and the second channel layer. A second conductive is disposed at one side of the second channel layer away from the storage node. A source line and a drain line are respectively disposed at opposite sides of the second channel layer in the second direction.