DRAM Memory Cell Layout With Wrapped Channel and Flat Capacitor
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Solution Overview
Problem
Current DRAM devices face challenges in increasing integration density while maintaining enhanced electric characteristics, particularly in efficiently arranging word lines, bit lines, channels, and capacitors.
Innovation Solution
A semiconductor device design that includes a bit line, a channel, a word line, and a capacitor, where the channel and capacitor are disposed at the same level as the word lines, reducing the vertical thickness of memory cells and enhancing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the vertical thickness of memory cells is reduced to increase integration density, then the integration degree increases, but the electric characteristics may deteriorate
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional structure by positioning the channel to surround the bit line in multiple directions. The channel extends along the bit line and wraps around it, creating a vertical and lateral presence that increases the effective area without increasing the footprint, thus improving integration density while maintaining electrical performance
Solution Approach 2:
The channel is designed to surround and wrap around the bit line, creating a nested configuration where the channel encloses the bit line. This nested structure maximizes the interaction area between the channel and bit line within a compact vertical space, achieving high integration density without compromising electrical characteristics
2Length of stationary object
If the channel and capacitor are disposed at the same level as word lines, then the vertical thickness is reduced, but the arrangement complexity increases
Solution Approach 1:
The patent merges the channel and capacitor into the same horizontal plane as the word lines, eliminating the need for separate vertical stacking. This consolidation reduces the overall vertical thickness of the memory cell while the systematic arrangement of components along the bit line maintains manufacturing feasibility
Solution Approach 2:
The memory cell is segmented into distinct functional regions along the bit line, with channels positioned at regular intervals and capacitors placed at specific locations. This segmentation allows for systematic manufacturing processes while achieving reduced vertical thickness through the flattened configuration
Data Source
AI summary
A semiconductor device includes a bit line, a channel, a word line and a capacitor. The bit line is disposed on a substrate, and extends in a first direction substantially perpendicular to an upper surface of the substrate. The channel at least partially surrounds a sidewall of the bit line. The word line is disposed on the substrate, and at least a portion of the word line overlaps the channel in a horizontal direction substantially parallel to the upper surface of the substrate. The capacitor is electrically connected to the channel, and at least a portion of the capacitor overlaps the channel and the word line in the horizontal direction.