Self-Managed DRAM Channel Puncturing to Cut Write Energy
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Solution Overview
Problem
The integration of self-managed DRAM modules leads to increased energy consumption due to high read/write amplification and inefficient memory utilization, particularly in systems with limited DRAM controllers and bandwidth.
Innovation Solution
Implementing techniques such as per-channel ECC codeword folding, per-channel ECC codeword puncturing, and coarse-grained compression to optimize energy efficiency by reducing read/write amplification and improving memory access throughput in self-managed DRAM modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If self-managed DRAM modules are implemented to expand memory capacity and enable sharing among multiple CPUs, then memory utilization efficiency and available bandwidth are improved, but energy consumption increases due to high read/write amplification
Solution Approach 1:
The patent divides each DDR channel into multiple sub-channels, where each sub-channel contains a subset of DRAM chips. This segmentation allows the management engine to selectively activate only the necessary sub-channels for each data access operation, reducing the number of DRAM chips that need to be read from or written to, thereby reducing read/write amplification and energy consumption while maintaining memory capacity and utilization efficiency.
2Reliability
If conventional ECC coding is used across all DRAM chips in a channel, then data reliability is maintained, but read/write operations require accessing all chips increasing energy consumption
Solution Approach 1:
The patent segments the ECC codeword storage across sub-channels, allowing the management engine to perform ECC encoding and decoding operations on subsets of DRAM chips rather than requiring access to all chips in a channel. This maintains data reliability through proper error correction while reducing the scope of read/write operations and associated energy consumption.
Solution Approach 2:
The patent applies different access patterns to different sub-channels based on the specific data access requirements. Each sub-channel can be independently managed with appropriate ECC protection, allowing the system to provide reliable data access with minimal energy consumption by activating only the locally necessary sub-channels rather than the entire channel.
3Quantity of substance
If DRAM capacity is expanded by adding more channels and chips, then available memory increases, but the number of DRAM controllers required increases leading to higher hardware complexity
Solution Approach 1:
The patent implements self-managed DRAM modules that can be shared among multiple CPUs, allowing a single DRAM module to serve multiple hosts. This multi-functionality enables the system to expand available memory capacity without proportionally increasing the number of DRAM controllers, as the same controller manages the same physical DRAM chips for multiple CPU instances, thereby reducing hardware complexity.
Data Source
AI summary
A self-managed DRAM module configured to reduce energy consumption. A module is described that includes a plurality of DDR channels, each DDR channel having a set of DRAM chips; and a management engine configured to read and write data blocks to DDR channels, wherein a write operation of a data block in a DDR channel is implemented according to a process that includes: compressing the data block to generate a compressed data block; encoding the compressed data block to obtain a punctured ECC codeword; determining a reduced number of DRAM chips in the DDR channel required to store the punctured ECC codeword; storing metadata indicative of the reduced number; and writing the punctured ECC codeword to the reduced number of DRAM chips in the DDR channel.