DRAM Circuitry with Discontinuous Material for Data Retention

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing memory technologies, particularly those using ferroelectric capacitors, face challenges in maintaining data retention due to the reversible nature of polarization states during read operations, requiring immediate rewriting of memory cells after reading.

Innovation Solution

The development of integrated circuitry constructions and methods for forming DRAM circuitry that include recessed access devices with buried access lines and conductive vias, where a discontinuous material is used between digitlines and conductive vias to facilitate stable memory cell states, reducing the need for immediate rewriting.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of stationary object

If ferroelectric capacitors are used in memory cells, then non-volatile storage capability is achieved, but data retention is compromised due to polarization reversal during read operations

Engineering Contradiction:
Improvedata retention timeVSAvoidmemory state stability
Core Design Contradiction:
Duration of action of stationary objectVSReliability

Solution Approach 1:

The memory cell is segmented into distinct functional regions: the ferroelectric capacitor for non-volatile storage, the access transistor for control, and the readout circuitry. This segmentation allows the ferroelectric material to maintain its polarization state independently while the access transistor controls read/write operations, reducing unwanted polarization reversal during reading.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

An intermediary readout mechanism is introduced that detects the polarization state of the ferroelectric capacitor without directly causing reversal. The read operation uses a sense amplifier to detect voltage changes caused by the ferroelectric state, allowing non-destructive reading that preserves data retention while maintaining reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If immediate rewriting is performed after reading ferroelectric memory cells, then data accuracy is maintained, but writing frequency increases reducing overall system efficiency

Engineering Contradiction:
Improvedata accuracyVSAvoidwrite operation frequency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The memory cell structure is designed with preliminary protection mechanisms where the access transistor and word line control are configured to prevent unintended polarization reversal during read operations. This preliminary action ensures data accuracy is maintained without requiring immediate rewriting, thus improving productivity by reducing write operation frequency.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If conventional memory cell structures are used, then manufacturing simplicity is maintained, but data retention and stability are insufficient for non-volatile applications

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoiddata retention time
Core Design Contradiction:
Ease of manufactureVSDuration of action of stationary object

Solution Approach 1:

The invention merges the volatile memory access structure with the non-volatile ferroelectric storage element into a unified memory cell. The ferroelectric capacitor is integrated directly with the access transistor using compatible manufacturing processes, combining the ease of manufacture of conventional memory with the non-volatile data retention capability, achieving both manufacturing simplicity and extended data retention time.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11411008B2Integrated circuity, dram circuitry, methods used in forming integrated circuitry, and methods used in forming DRAM circuitry
Publication Date: 2022.08.09 MICRON TECHNOLOGY INC
  • US11411008B2 patent drawing
  • US11411008B2 patent drawing
  • US11411008B2 patent drawing

AI summary

A method used in forming integrated circuitry comprises forming a plurality of conductive vias comprising conductive material. The conductive vias are spaced relative one another by intermediate material. A discontinuous material is formed atop the conductive material of the vias and atop the intermediate material that is between the vias. Metal material is formed atop, directly against, and between the discontinuous material and atop and directly against the conductive material of the vias. The metal material is of different composition from that of the discontinuous material and is above the intermediate material that is between the vias. The metal material with discontinuous material there-below is formed to comprise a conductive line that is atop the intermediate material that is between the vias and is directly against individual of the vias. Structures independent of method are disclosed.