Phase Adjustment Circuit for DRAM 90-Degree Clock Skew Correction
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Solution Overview
Problem
The mismatch and noise caused by phase skew in the four clock paths of a Dynamic Random Access Memory (DRAM) due to differing phases by 90 degrees affect the memory's performance.
Innovation Solution
A phase adjusting circuit that includes a detection module to detect phase differences, a comparison module for duty cycle comparison, a counting module to count pulses, and an adjustment module to adjust clock signals to ensure a preset phase difference, thereby correcting phase skew between clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If four clock paths with 90-degree phase differences are used in DRAM, then clock timing diversity is improved, but phase skew causes mismatch and noise
Solution Approach 1:
The patent employs a feedback mechanism where the detection module continuously monitors phase differences between clock signals, compares them against reference values, and generates control signals to adjust delay elements. This closed-loop feedback system dynamically compensates for phase skew, maintaining accurate 90-degree phase relationships despite variations in operating conditions, thereby resolving the contradiction between clock timing diversity and signal accuracy.
Solution Approach 2:
The patent adjusts the delay parameter of delay elements based on detected phase differences. By dynamically changing the delay parameter in response to measured phase skew, the system maintains accurate phase relationships between clock signals. This parameter adjustment approach allows the system to adapt to different operating conditions while preserving signal integrity, thus resolving the contradiction between productivity and reliability.
2Measurement precision
If phase skew correction is implemented, then signal accuracy is improved, but device complexity increases
Solution Approach 1:
The patent divides the phase correction function into distinct modular components: a detection module for measuring phase differences, a comparison module for referencing against standard values, and adjustment modules with delay elements for correction. This segmentation allows each component to perform its function efficiently and independently, reducing overall system complexity while maintaining high measurement precision and correction accuracy.
Solution Approach 2:
The phase correction system is self-regulating, using its own output signals as inputs for detection and comparison. The detection module automatically measures phase differences between clock signals, and the control signals generated are fed back to adjust the delay elements without external intervention. This self-service mechanism simplifies the control architecture while achieving precise phase accuracy.
Data Source
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AI summary
Embodiments of the present disclosure provide a phase adjusting circuit, a delay locking circuit, and a memory. The phase adjusting circuit includes a detection module, a comparison module, a counting module, and an adjustment module that are connected in sequence. Herein, the detection module is configured to detect a phase difference between a first clock signal and a second clock signal to obtain a first detection signal and a second detection signal. The comparison module is configured to perform duty cycle comparison of the first detection signal and the second detection signal to obtain a counting indication signal. The counting module is configured to count a number of pulses of a preset counting clock signal based on the counting indication signal to obtain a count value. The adjustment module is configured to perform phase adjustment of the second clock signal based on the count value, so that the phase difference between the first clock signal and the second clock signal is a preset value.