In-Memory Column Selection for DRAM Computation Without Extra Logic
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Solution Overview
Problem
Existing DRAM devices with internal processors for computing operations require separate processors or arithmetic logic units, increasing cost and chip size while consuming additional power.
Innovation Solution
A memory device with integrated computation functionality, utilizing a first and second cell array, bit line sense amplifiers, and column selection circuits to perform computations without a separate arithmetic processor or logic unit, through repeated internal read operations and lookup table-based bit-serial computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a separate processor or arithmetic logic unit is added to enable computation function, then computation capability is improved, but device complexity and chip size increase
Solution Approach 1:
The patent merges the computation function with the memory device by integrating column selection circuits that can operate in both traditional column selection mode and computation mode. The same hardware infrastructure (memory cells, bit lines, sense amplifiers, and column selection circuits) is used for both storage and computation operations, eliminating the need for separate processors or arithmetic logic units.
Solution Approach 2:
The column selection circuits are designed with multi-functionality, capable of performing both traditional column selection operations and computation operations. By controlling the column selection circuits with compute selection signals, the same hardware can dynamically switch between memory access functions and arithmetic operations, achieving versatility without increasing device complexity.
2Adaptability or versatility
If a separate processor or arithmetic logic unit is added to enable computation function, then computation capability is improved, but manufacturing cost increases
Solution Approach 1:
The computation function is merged into the existing memory device structure, utilizing already-present components (memory cells, bit lines, sense amplifiers, column selection circuits). This approach avoids the need for additional processors or arithmetic logic units, thereby reducing manufacturing complexity and cost while enabling computation capability.
Solution Approach 2:
The column selection circuits are designed to perform multiple functions: traditional column selection for memory access and computation operations when activated by compute selection signals. This multi-functionality eliminates the need for separate computation hardware, reducing manufacturing costs while providing versatile computation capability.
3Adaptability or versatility
If additional hardware components are added for computation, then computation function is improved, but power consumption increases
Solution Approach 1:
The computation operations are performed using the existing memory device hardware (memory cells, bit lines, sense amplifiers, column selection circuits) rather than adding separate computation units. This merging approach ensures that computation power consumption is included in the baseline memory device power consumption, avoiding additional power overhead from separate processors or arithmetic logic units.
Solution Approach 2:
The column selection circuits are designed to handle both column selection and computation tasks. When computation mode is activated via compute selection signals, the same hardware infrastructure performs arithmetic operations, ensuring that no additional dedicated computation hardware is powered up, thereby avoiding extra power consumption.
Data Source
AI summary
A memory device with a computation function includes a first cell array including first memory cells connected to word lines, a second cell array including second memory cells connected to the word lines, a first bit line sense amplifier that sense first voltages of first bit lines connected to the first memory cells, a second bit line sense amplifier that senses second voltages of second bit lines connected to the second memory cells, a first column selection circuit that outputs a first output signal among the first voltages based on a first column compute selection signal, a second column selection circuit that outputs a second output signal among the second voltages based on a second column compute selection signal different from the first column compute selection signal, and a column compute control circuit that generates the first column compute selection signal and the second column compute selection signal.


