DRAM Command Address Training Without a Dedicated CKE Pin
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Solution Overview
Problem
Existing DRAM command address interface training techniques require an additional clock enable (CKE) pin, increasing system complexity and power consumption, and are non-continuous, leading to longer training times.
Innovation Solution
The proposed method eliminates the need for a CKE pin by using a continuous pseudo-random binary sequence (PRBS) pattern for training, allowing the memory controller to initialize and compare data patterns without a dedicated CKE pin, enabling continuous training without gaps in sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock enable (CKE) pin is used for command address interface training, then training can be performed, but system complexity and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the CKE pin from the training interface by using existing command address pins to carry training data. The memory controller transmits training patterns through normal command address pathways, removing the need for dedicated training pins and their associated control logic.
Solution Approach 2:
The patent makes existing command address pins multi-functional by using them both for normal memory operations and for training data transmission. The same pins that carry command addresses during normal operation are utilized to carry training patterns during training mode, eliminating the need for separate dedicated training pins.
2Reliability
If a clock enable (CKE) pin is used for command address interface training, then training can be performed, but power consumption increases
Solution Approach 1:
The patent extracts and eliminates the CKE pin from the training interface by using existing command address pins to carry training data. The memory controller transmits training patterns through normal command address pathways, removing the need for dedicated training pins and their associated control logic.
Solution Approach 2:
The patent makes existing command address pins multi-functional by using them both for normal memory operations and for training data transmission. The same pins that carry command addresses during normal operation are utilized to carry training patterns during training mode, eliminating the need for separate dedicated training pins.
3Reliability
If non-continuous training operation is used, then sampling can be controlled, but training time increases
Solution Approach 1:
The patent enables continuous training operation where the memory device continuously samples and processes training patterns without interruption. The training pattern is continuously transmitted through the command address pins, allowing uninterrupted sampling and faster convergence compared to periodic or gated sampling approaches.
Solution Approach 2:
The memory device is pre-configured with the capability to continuously sample command address pins, so that when training mode is initiated, the sampling is already in progress and can continue without interruption. This preliminary preparation enables immediate continuous training without setup delays.
Data Source
AI summary
Various embodiments include a memory device that is capable of performing command address interface training operations, to determine that certain timing conditions are met, with fewer I/O pins relative to prior approaches. Prior approaches for command address interface training involve loading data via a set of input pins, a clock signal, and a clock enable signal that identifies when the input pins should be sampled. Instead, the disclosed memory device generates a data pattern within the memory device that matches the data pattern continuously being transmitted to the memory device by an external memory controller. The memory device compares the generated data pattern with the received data pattern and transmits the result of the comparison on one or more data output pins. The memory controller receives and analyzes the result of the comparison to determine whether the command address interface training passed or failed.