DRAM Common Electrode Layout for Tighter Memory Array Spacing
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Solution Overview
Problem
The configuration of common electrodes in current DRAMs limits the scaling down of memory chip size due to the need for separate functional devices between adjacent memory arrays.
Innovation Solution
A memory design where multiple memory arrays share a common electrode, with a common electrode contact plug and vertical transistors on the same side, allowing other functional devices to be placed at the periphery, reducing the space between arrays and facilitating chip size reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If common electrodes corresponding to different memory arrays are separated from each other with other functional devices disposed between adjacent memory arrays, then the functional devices can be properly positioned, but the size of memory chips cannot be scaled down
Solution Approach 1:
The patent merges the common electrodes of different memory arrays into a single shared structure. Multiple memory arrays share the same common electrode, eliminating the need for separate functional devices between arrays. This consolidation reduces the overall chip area while maintaining proper functional device positioning through the shared electrode architecture.
Solution Approach 2:
The common electrode structure is designed to serve multiple memory arrays simultaneously. A single common electrode performs the function of what would traditionally require separate electrodes for each memory array, enabling one structure to fulfill multiple roles and reduce the total component count and chip area.
2Reliability
If common electrodes corresponding to different memory arrays are separated from each other, then the functional devices can be disposed between adjacent memory arrays, but the manufacturing process becomes more complex
Solution Approach 1:
By combining multiple common electrodes into a single shared structure, the patent reduces the number of manufacturing steps required. Instead of fabricating separate electrodes for each memory array and positioning functional devices between them, the shared electrode structure simplifies the fabrication process while still enabling proper functional device placement.
3Reliability
If common electrodes corresponding to different memory arrays are separated from each other, then the functional devices can be disposed between adjacent memory arrays, but the device complexity increases
Solution Approach 1:
The patent merges multiple common electrode structures into a single shared electrode that serves multiple memory arrays. This consolidation reduces the overall device complexity by eliminating redundant components and simplifying the interconnections between memory arrays and functional devices.
Solution Approach 2:
The shared common electrode structure is designed to universally serve multiple memory arrays simultaneously, reducing the overall device complexity. One electrode structure performs the function of what would traditionally require multiple separate electrodes, simplifying the overall device architecture.
Data Source
AI summary
A memory includes a first semiconductor structure and a second semiconductor structure coupled to the first semiconductor structure. The first semiconductor structure includes a plurality of memory arrays arranged in an array and spaced apart from each other, each memory array includes a plurality of memory cells arranged in an array, each memory cell includes a vertical transistor extending in a first direction and a capacitor coupled to the vertical transistor, the capacitor includes a first electrode and a second electrode opposite to each other, and the first electrode is coupled to the vertical transistor; the second semiconductor structure includes a peripheral circuit and is disposed on a side of the vertical transistor away from the capacitor in the first direction; the first semiconductor structure further includes a common electrode electrically connected to the second electrodes of the capacitors in the plurality of memory arrays.