DRAM Compute-in-Memory Circuit With Shared Bit Lines
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Solution Overview
Problem
Existing memory arrays face challenges in efficiently performing computations due to the need for data movement between memory and computation circuits, leading to increased area and power consumption, especially in complex operations like convolutional neural networks.
Innovation Solution
A memory circuit design with a DRAM array separated by a boundary layer from a computation circuit, utilizing via structures for electrical connections, enabling computation-in-memory operations with high memory capacity, reduced area, and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data bits are moved between memory arrays and computation circuits to perform operations, then computation functionality is achieved, but area and power consumption increase
Solution Approach 1:
The patent merges memory and computation functions into a single integrated circuit block. The memory array and computation circuit share the same physical substrate and are interconnected through shared bit lines, eliminating the need for separate data movement paths. This integration directly reduces the total area required while enabling computation functionality.
Solution Approach 2:
The bit lines serve multiple functions: they act as storage elements for data bits and simultaneously as computation elements for performing logical operations. This multi-functionality eliminates the need for dedicated data movement pathways, reducing overall circuit area while maintaining full computation capability.
2Productivity
If data bits are moved between memory arrays and computation circuits to perform operations, then computation functionality is achieved, but power consumption increases
Solution Approach 1:
The integration of memory and computation circuits eliminates the need for physical data movement between separate components. Data remains within the memory array structure throughout the computation process, eliminating the power consumption associated with data transfer operations while maintaining full computation functionality.
Solution Approach 2:
The bit lines perform dual roles as both storage and computation elements. By keeping data in place and using it directly for computation operations, the system eliminates the energy expenditure required for data movement while achieving the desired computational results.
3Productivity
If multiple layers of operations are performed with results used as input for subsequent operations, then complex computation is achieved, but data movement complexity increases
Solution Approach 1:
The patent combines memory and computation functions within the same circuit block, allowing multiple layers of operations to be performed in-place without requiring complex data movement between separate components. Results from one operation remain in the memory array and are directly available for subsequent operations, simplifying the overall system architecture.
Data Source
AI summary
A memory circuit includes a boundary layer, a first circuit positioned on a first side of the boundary layer and including a DRAM array including a plurality of DRAM cells, a second circuit positioned on a second side of the boundary layer opposite the first side and including a computation circuit, the computation circuit including a sense amplifier circuit, and a plurality of bit lines coupled to the plurality of DRAM cells and the sense amplifier circuit. Each bit line of the plurality of bit lines includes a via structure positioned in the boundary layer and the plurality of DRAM cells of the first circuit positioned on the first side of the boundary layer is an entirety of the DRAM cells of the memory circuit coupled to the sense amplifier circuit.