DRAM Read/Write Circuit With Conditional Data-Line Precharge
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Solution Overview
Problem
In dynamic random access memory (DRAM) systems, the data line is precharged to the supply voltage between pseudo read and write back operations, leading to current waste and reduced data write speed in mask write mode.
Innovation Solution
A read/write circuit with a control circuit that stops precharging the data line after data read and before data write when in mask write mode, and precharges the data line before data write when not in mask write mode, thereby optimizing current usage and write speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data line is precharged to the supply voltage between pseudo read and write back operations, then the data line is ready for the next operation, but current is wasted and data write speed is reduced
Solution Approach 1:
The patent applies dynamics by making the precharge operation conditional rather than static. The control circuit dynamically adjusts whether to perform precharging based on the operation type (mask write vs. normal write). For mask write operations, the precharge is skipped or cancelled, while for normal write operations, precharge is performed. This dynamic adaptation resolves the contradiction by eliminating unnecessary energy consumption while maintaining data line readiness when needed.
Solution Approach 2:
The patent changes the operational parameters of the data line precharge based on the operation mode. By detecting whether a mask write or normal write operation is being performed, the system adjusts the precharge parameter (performing or skipping precharge) to optimize between reliability and energy efficiency. This parameter change allows the system to avoid wasting current on mask write operations while ensuring proper preparation for normal write operations.
2Reliability
If the data line is precharged to the supply voltage between pseudo read and write back operations, then the data line is ready for the next operation, but the data write speed is reduced
Solution Approach 1:
The system dynamically adjusts the precharge timing and execution based on the operation type. For mask write operations, the precharge step is skipped or cancelled, allowing the write operation to proceed immediately after pseudo read, thus increasing write speed. For normal write operations, the precharge is performed to ensure data line readiness. This dynamic control resolves the contradiction between reliability and productivity.
Solution Approach 2:
The patent selectively applies preliminary action (precharging) only when necessary. By determining the operation type in advance, the system performs precharge only for normal write operations where it is needed for reliability, while skipping it for mask write operations where it would only delay the write process. This selective preliminary action optimizes both data line readiness and write speed.
Data Source
AI summary
Provided are a read/write circuit, a read/write method, and a memory. The read/write circuit includes: a write driver circuit, configured to: precharge a data line, and write to-be-written data into the data line; and a control circuit, when in a mask write mode, the control circuit being configured to control the write driver circuit to stop precharging the data line after data read and before data write, and when not in the mask write mode, the control circuit being configured to control the write driver circuit to precharge the data line before data write.