Recessed DRAM Conductor Step Profile for Lower GIDL

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Solution Overview

Problem

Recessed access devices in DRAMs face issues with gate-induced drain leakage (GIDL) due to a flat top surface of conductors and high resistance when the capping layer is thicker, which affects performance.

Innovation Solution

A semiconductor structure with a concave substrate featuring a conductor having a stepped surface, where the first top surface is closer to the dielectric layer, and a capping layer with specific surface and bottom surface configurations, along with a manufacturing method involving a sacrificial layer and etching processes to achieve these configurations, reducing GIDL and resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the proportion of the conductor is larger with a flat top surface, then the resistance is reduced, but gate-induced drain leakage (GIDL) problems occur

Engineering Contradiction:

ImproveresistanceVSAvoidgate-induced drain leakage

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies curvature by forming a stepped surface on the conductor instead of a flat top surface. The stepped surface includes a first level and a second level at different heights, creating a non-planar geometry that reduces the electric field concentration at the conductor-dielectric interface, thereby reducing GIDL while maintaining low resistance

Inventive Principle:

Principle #14Spheroidality (Curvature)

Solution Approach 2:

The conductor's top surface is segmented into multiple levels (first level and second level) rather than being a single flat surface. This segmentation allows different portions of the conductor to have different functions: the lower portion maintains electrical connectivity while the stepped structure reduces harmful electric field effects

Inventive Principle:

Principle #1Segmentation

2Object-affected harmful factors

If the proportion of the capping layer is larger, then the GIDL problem is reduced, but the resistance increases

Engineering Contradiction:

Improvegate-induced drain leakageVSAvoidresistance

Core Design Contradiction:

Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent applies local quality by creating different regions on the conductor surface with different properties. The stepped surface provides local variations in height and exposed conductor area, allowing the structure to simultaneously achieve low resistance (through sufficient conductor exposure) and reduced GIDL (through the stepped geometry that reduces electric field concentration)

Inventive Principle:

Principle #3Local quality

3Ease of manufacture

If a flat top surface of the conductor is used, then the manufacturing is simplified, but GIDL problems occur

Engineering Contradiction:

Improveconductor formationVSAvoidgate-induced drain leakage

Core Design Contradiction:

Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The stepped surface structure is formed during the conductor formation process itself, rather than requiring subsequent complex processing. The conductor is deposited and then selectively etched or planarized to create the stepped levels, integrating the GIDL reduction feature into the base manufacturing flow without adding significant complexity

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The semiconductor structure reduces gate-induced drain leakage and achieves a low resistance feature, enhancing performance in subsequent applications.

Implementation Method 1

etching the conductor such that the conductor is located in the concave portion; etching the second portion of the sacrificial layer and the conductor such that the conductor has a first top surface and a second top surface

Methodology Applied

Scientific EffectEtching:

Data Source

PatentUS11967628B2Manufacturing method of semiconductor structure

Publication Date: 2024.04.23 NAN YA TECH

AI summary

A semiconductor structure includes a substrate, an isolation layer, a dielectric layer, an insulation layer, a conductor and a capping layer. The substrate has a concave portion. The isolation layer is located on a top surface of the substrate. The dielectric layer is located on the isolation layer. The insulation layer is located on a surface of the concave portion and extends to a sidewall of the isolation layer. The conductor is located on the insulation layer in the concave portion. The conductor has a first top surface and a second top surface, and the first top surface is closer to the dielectric layer than the second top surface. The capping layer is located in the concave portion and covers the conductor.