DRAM Active Area Structure with Contact Enhancement Caps
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Solution Overview
Problem
The reduction of active area size in DRAM cells to increase storage density leads to increased contact resistance due to lithography overlay issues, compromising the performance of DRAM devices.
Innovation Solution
The implementation of a memory array structure with trench-defined active areas of varying heights, where a recessed group of active areas has contact enhancement sidewall spacers or caps to increase the landing area for capacitor contacts, enhancing electrical contact and reducing interference between adjacent cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the active area size is reduced to increase storage density, then the storage capability is improved, but the contact resistance increases due to lithography overlay issues
Solution Approach 1:
The patent introduces a vertical dimension by forming a trench around the active area and filling it with an isolation structure. This creates a three-dimensional configuration where the active area is laterally separated from adjacent cells, allowing the capacitor contact to be positioned on the active area top surface without lateral interference from neighboring cells, thus reducing contact resistance while maintaining high storage density
Solution Approach 2:
The patent segments the semiconductor substrate by forming trenches that laterally separate adjacent active areas. This segmentation creates independent regions for each memory cell, preventing interference between adjacent cells and ensuring that capacitor contacts are electrically isolated, which reduces contact resistance and improves reliability
2Quantity of substance
If the active area size is minimized to achieve high storage density, then the storage capability is improved, but the landing area for capacitor contact is reduced
Solution Approach 1:
The patent utilizes the vertical dimension by forming a trench around the active area and filling it with an isolation structure that extends above the active area top surface. This creates additional vertical space that can be used for the capacitor contact structure, effectively increasing the landing area without expanding the lateral footprint of the active area, thus maintaining high storage density while improving contact area
3Quantity of substance
If the active areas are closely spaced to increase storage density, then the storage capability is improved, but interference between adjacent memory cells increases
Solution Approach 1:
The patent segments adjacent active areas by forming trenches filled with isolation structures that laterally separate them. This segmentation creates physical and electrical barriers between adjacent memory cells, preventing signal interference and capacitive coupling between neighboring cells, thus allowing closely spaced active areas to achieve high storage density without suffering from cell-to-cell interference
Solution Approach 2:
The isolation structure formed in the trench acts as an intermediary between adjacent active areas. This intermediate structure provides electrical isolation and prevents direct interaction between neighboring memory cells, reducing interference while allowing the active areas to be closely spaced for high storage density
Data Source
AI summary
The present disclosure provides a dynamic random access memory (DRAM) array. The memory array includes a semiconductor substrate, an isolation structure and contact enhancement sidewall spacers. The semiconductor substrate has a trench defining laterally separate active areas formed of surface regions of the semiconductor substrate. Top surfaces of a first group of the active areas are recessed with respect to top surfaces of a second group of the active areas. The isolation structure is filled in the trench and in lateral contact with bottom portions of the active areas. The contact enhancement sidewall spacers laterally surround top portions of the active areas, respectively.