DRAM Contact Layer Patterning With Protection Layers

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Solution Overview

Problem

The manufacturing process of Dynamic Random Access Memory (DRAM) is complex due to the difficulty in forming contact layers with poor electrical performance, often resulting in concave morphologies on the sidewalls that increase resistance and reduce performance as feature sizes decrease.

Innovation Solution

A method involving the formation of an initial contact layer and an initial protection layer in a stacked structure within grooves between bit lines, where the protection layer reduces the height of the contact layer, simplifying the patterning process and reducing sidewall erosion, thereby improving the electrical performance by maintaining a vertical morphology.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If the feature size of DRAM is reduced to increase integration level, then the integration level is improved, but the manufacturing difficulty increases and performance deteriorates

Engineering Contradiction:
Improveintegration levelVSAvoidmanufacturing difficulty
Core Design Contradiction:
Area of moving objectVSEase of manufacture

Solution Approach 1:

The contact layer formation process is segmented into multiple steps: forming an initial contact layer filling the groove, then forming a protection layer on top, and finally performing patterning. This segmentation allows better control over each step, particularly preventing sidewall erosion during patterning while maintaining the required contact layer dimensions for high integration density

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The protection layer is formed in advance on the initial contact layer before patterning occurs. This preliminary action protects the contact layer sidewalls from erosion during the patterning process, ensuring that the contact layer maintains its vertical morphology and proper dimensions even as feature sizes are reduced for higher integration

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If conventional contact layer formation is used, then the process is simple, but concave morphologies form on sidewalls increasing resistance and reducing electrical performance

Engineering Contradiction:
Improveprocess simplicityVSAvoidelectrical performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

A protection layer is introduced as an intermediary between the initial contact layer and the patterning process. This protection layer acts as a mediator that prevents direct exposure of the contact layer sidewalls to etching, thereby avoiding concave morphology formation while maintaining process feasibility. The protection layer is subsequently removed after serving its protective function

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The method changes the physical state and dimensions of the contact layer formation by controlling the initial contact layer to fill the groove completely, then using the protection layer to maintain vertical sidewalls during patterning. This parameter control ensures the contact layer maintains optimal electrical properties without concave deformations

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If the height of contact layer is reduced to simplify patterning, then patterning complexity is reduced, but contact layer resistance increases

Engineering Contradiction:
Improvepatterning complexityVSAvoidcontact layer resistance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The solution moves from controlling only the horizontal dimensions to incorporating vertical dimension control through the protection layer. By forming the protection layer on top of the initial contact layer, the method creates a multi-layer structure that simplifies patterning while maintaining the contact layer height and vertical morphology necessary for low resistance

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12150294B2Method for manufacturing semiconductor structure and same
Publication Date: 2024.11.19 CHANGXIN MEMORY TECH INC
  • US12150294B2 patent drawing
  • US12150294B2 patent drawing
  • US12150294B2 patent drawing

AI summary

A method for manufacturing a semiconductor structure includes: providing a base, in which a plurality of bit lines extending in a first direction and a groove located between two adjacent ones of the bit lines are provided on the base; forming an initial contact layer and an initial protection layer filling the groove, in which the initial contact layer is in contact with the base, the initial protection layer is located on the initial contact layer; patterning the initial contact layer and the initial protection layer to form contact layers that are discrete from each other and protection layers that are discrete from each other; and forming a dielectric layer between two adjacent ones of the contact layers, in which the dielectric layer is further located between two adjacent ones of the protection layers, a material of the dielectric layer is different from a material of the protection layer.