3D DRAM Contact Structures for Misalignment-Tolerant Interconnects
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Solution Overview
Problem
Microelectronic device designers face challenges in reducing the size and improving the performance of memory devices, such as DRAM, due to processing conditions and the configuration of control logic devices, which limit the reduction of feature dimensions and enhancement of performance metrics like speed and power consumption.
Innovation Solution
The solution involves a microelectronic device structure with a first microelectronic device attached to a second, where the second structure includes control logic devices vertically overlying memory cells and features like tapered contact structures in digit and word line exit regions to facilitate tighter pitches and larger landing areas, enabling better alignment and electrical connections despite misalignment errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control logic devices are provided in the base control logic structure to control DRAM cell operations, then the memory device can perform required control functions, but the processing conditions and device configurations limit further reduction of the memory device size and improvement of performance metrics
Solution Approach 1:
The patent moves control logic devices from the planar base control logic structure to a vertical arrangement directly overlying memory cells in the stack. This dimensional transition from 2D to 3D spatial organization reduces the horizontal footprint and allows tighter pitch between features while maintaining control functionality.
Solution Approach 2:
The control logic functionality is segmented into multiple discrete control logic devices that can be individually positioned and optimized. Each control logic device is separately formed and can be selectively placed to control specific memory cells, allowing flexible configuration and reduced overall complexity.
2Productivity
If feature dimensions are reduced to increase integration density, then more features can be packed into the memory device, but processing conditions limit the minimum achievable feature dimensions
Solution Approach 1:
The patent transitions from planar feature arrangement to vertical stacking, allowing integration density to increase by utilizing the vertical dimension. This enables higher density without requiring proportionally smaller lateral feature dimensions, thereby circumventing the limits of current lithographic processing capabilities.
Solution Approach 2:
The patent changes the spatial arrangement parameter from two-dimensional to three-dimensional configuration. By stacking memory cells and control logic devices vertically, the design achieves higher integration density while maintaining feature dimensions that are compatible with existing manufacturing precision capabilities.
3Productivity
If separation distance between neighboring features is reduced to increase density, then more features can be integrated, but alignment errors become more significant
Solution Approach 1:
The patent utilizes vertical stacking to achieve higher density without proportionally reducing lateral separation distances. The vertical arrangement allows tighter effective pitch between functional elements while maintaining sufficient lateral spacing for accurate alignment during manufacturing processes.
Solution Approach 2:
The patent introduces intermediate structures such as contact structures and routing layers that facilitate precise alignment between vertically stacked features. These intermediary elements act as alignment references and coupling mechanisms, enabling accurate registration despite reduced overall device dimensions.
4Reliability
If quantities and dimensions of control logic devices are increased to improve control functionality, then better memory cell control is achieved, but the horizontal footprint of the memory device increases
Solution Approach 1:
The patent relocates control logic devices from the horizontal plane to the vertical dimension, stacking them directly over memory cells. This vertical arrangement dramatically reduces the horizontal footprint while maintaining or enhancing control capability through increased proximity and direct coupling to memory cells.
Solution Approach 2:
The patent implements a nested arrangement where control logic devices are positioned within or directly over the vertical projection of memory cell structures. This nesting approach allows control logic to be integrated within the same vertical space occupied by memory cells, minimizing additional horizontal footprint.
Data Source
AI summary
A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure attached to the first microelectronic device structure. The first microelectronic device structure comprises memory arrays comprising memory cells comprising access devices and storage node devices, digit lines coupled to the access devices and extending in a first direction to a digit line exit region, and word lines coupled to the access devices and extending in a second direction to a word line exit region. The second microelectronic device structure comprises control logic devices over and in electrical communication with the memory cells. The microelectronic device further comprises contact structures individually in contact with the digit lines in the digit line exit region and in electrical communication with at least some of the control logic devices, at least one of the contact structures comprising a first cross-sectional area at an interface of the first microelectronic device structure and the second microelectronic device structure, and a second cross-sectional area at an interface of one of the digit lines and the at least one of the contact structures, the second cross-sectional area smaller than the first cross-sectional area. Related microelectronic devices, memory devices, electronic systems, and methods are also described.