DRAM Contact Plug and Landing Pad Layout for Fewer Lithography Steps
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Solution Overview
Problem
As DRAM devices become increasingly integrated, the reduction in pattern dimensions and increase in arrangement density lead to a higher number of photolithography processes, which can result in pattern defects.
Innovation Solution
The semiconductor device includes a substrate with a cell region and a core/peripheral region, featuring bit line structures, gate structures, contact plugs, and landing pad patterns. The contact plugs are stacked vertically, and the landing pad patterns are electrically connected to the contact plugs, allowing for reduced operations in manufacturing through a single photo process using EUV light.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of photolithography processes is increased to achieve higher integration density, then the arrangement density of patterns is improved, but the risk of pattern defects increases
Solution Approach 1:
The patent merges multiple photolithography processes into a single process by forming both the bit line electrode pattern and the capacitor electrode pattern simultaneously. This is achieved by applying a combined photoresist pattern that covers both regions, followed by a single etching process that creates both electrode structures in one operation, thereby reducing the total number of photolithography steps while maintaining high integration density.
Solution Approach 2:
The patent employs a universal photoresist pattern design that serves multiple functions: it defines both the bit line electrode pattern in the transistor region and the capacitor electrode pattern in the capacitor region simultaneously. The same photoresist layer and etching process are used to create both structures, making the photolithography process multi-functional and reducing the overall process count.
2Manufacturing precision
If the number of photolithography processes is increased to form complex patterns, then the manufacturing precision of individual patterns is improved, but the total manufacturing complexity increases
Solution Approach 1:
The patent combines the formation of bit line electrodes and capacitor electrodes into a single photolithography process. A unified photoresist pattern is applied that simultaneously defines both electrode structures, and a single etching process creates both patterns. This merging approach maintains manufacturing precision for both structures while reducing the total number of photolithography processes from multiple steps to just one.
3Reliability
If more photolithography processes are used to reduce pattern defects, then the reliability of pattern formation is improved, but the manufacturing time and cost increase
Solution Approach 1:
The patent merges multiple sequential photolithography processes into a single simultaneous process. By applying a combined photoresist pattern that defines both bit line and capacitor electrode structures, and using a single etching process to form both patterns, the manufacturing cycle time is significantly reduced while maintaining high pattern formation reliability through optimized process parameters.
Data Source
AI summary
A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.