Dual-Layer DRAM Contact Plug Structure to Prevent Bridging
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Solution Overview
Problem
As the integration density of DRAM devices increases, forming contact plug structures between bit line structures becomes challenging due to reduced distance, leading to difficulties in preventing bridging and necking phenomena and maintaining electrical characteristics.
Innovation Solution
The semiconductor device employs a dual-layer upper contact plug structure formed through separate etching processes for the lower and upper portions, using a positive patterning process for the lower portion and a damascene process for the upper portion, reducing metal removal and residue, and incorporating insulation patterns to alleviate bridging and necking issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the integration degree of the DRAM device increases, then the device density improves, but the distance between bit line structures decreases making contact plug formation difficult
Solution Approach 1:
The upper contact plug is divided into two separate structures: a first upper contact plug and a second upper contact plug. This segmentation allows each contact plug to be formed through independent etching processes, enabling precise control over their respective shapes and positions, thereby solving the manufacturing difficulty caused by reduced spacing between bit line structures
Solution Approach 2:
The patent introduces vertical layering by stacking the first and second upper contact plugs in the depth direction. This dimensional approach allows contact plugs to be formed at different vertical levels, effectively utilizing the third dimension to maintain proper contact formation even when horizontal spacing between bit lines is reduced
2Ease of manufacture
If a single patterning process is used to form the upper contact plug, then the manufacturing process is simpler, but bridging and necking phenomena occur
Solution Approach 1:
The upper contact plug formation process is segmented into two separate etching operations: one for the first upper contact plug and another for the second upper contact plug. This process segmentation enables independent optimization of each etching step, preventing bridging and necking phenomena that would occur in a single patterning process while maintaining reasonable manufacturing complexity
Solution Approach 2:
The first upper contact plug is formed in advance before forming the second upper contact plug. This preliminary action allows the first contact plug to serve as a reference structure, enabling better control over the positioning and shape of the second contact plug, thereby preventing bridging and necking issues
3Quantity of substance
If the distance between bit line structures is reduced, then the device integration increases, but electrical shorts between contact plugs may occur
Solution Approach 1:
By stacking the first and second upper contact plugs vertically, the patent utilizes the depth dimension to separate contact paths. This vertical separation ensures that even when horizontal spacing between bit lines is reduced for higher integration, electrical isolation is maintained through the layered structure, preventing shorts between adjacent contact plugs
Data Source
AI summary
A semiconductor device includes an active pattern on a substrate; a gate structure extending through an upper portion of the active pattern; a bit line structure on a central portion of the active pattern; a lower contact plug on each of opposite end portions of the active pattern; and an upper contact plug structure on the lower contact plug. The upper contact plug structure includes a first upper contact plug and a second upper contact plug on the first upper contact plug. The second upper contact plug contacts the first upper contact plug. The first upper contact plug includes a first metal pattern and a barrier pattern covering a lower surface and a sidewall of the first metal pattern. An upper surface of the bit line structure contacts a lower surface of the second upper contact plug and does not contact the barrier pattern.


