DRAM Contact Plug Formation via Dual Etching and Doped Oxide Layer
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Solution Overview
Problem
Current DRAM units with buried gate structures face limitations in fabrication capability, affecting performance and reliability, particularly in forming effective contact plugs within semiconductor devices.
Innovation Solution
A method involving the formation of a semiconductor device with a contact plug structure that includes a dielectric layer, a doped oxide layer, and an oxide layer, where a first etching process creates a first contact hole and a second etching process expands the doped oxide layer to form a second contact hole with step-shaped sidewalls, allowing for the formation of an air gap within the conductive layer, enhancing the filling efficiency of conductive materials and the structural integrity of the contact plug.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single etching process is used to form contact holes, then fabrication process is simple, but contact plug formation success rate is low and manufacturing precision is insufficient
Solution Approach 1:
The patent divides the contact hole formation process into two distinct etching steps: a first etching process that forms an initial contact hole through the dielectric layer, and a second etching process that expands the contact hole through the doped oxide layer. This segmentation allows each etching step to be optimized independently, improving overall manufacturing precision while managing process complexity through systematic breakdown of the fabrication sequence.
Solution Approach 2:
The patent introduces a doped oxide layer between the dielectric layer and the contact pad before etching. This preliminary action creates a sacrificial layer that facilitates controlled etching and enables the formation of step-shaped sidewalls. The doped oxide layer is prepared in advance to enable subsequent precise etching operations and ensure proper contact plug formation.
2Ease of manufacture
If contact holes are formed directly in dielectric layer, then process steps are reduced, but filling efficiency of conductive materials is poor and structural integrity is compromised
Solution Approach 1:
The patent introduces a doped oxide layer as an intermediary between the dielectric layer and the contact pad. This intermediary layer serves multiple functions: it facilitates controlled etching, enables step-shaped sidewall formation, and provides a transition zone that improves conductive material filling. The doped oxide layer acts as a mediator that resolves the conflict between ease of manufacture and structural integrity.
Solution Approach 2:
The patent creates step-shaped sidewalls in the contact hole through selective etching of the doped oxide layer. This local quality change provides different geometries at different depths of the contact hole, with wider openings at the top for better material filling and narrower regions at the bottom for proper contact formation. The varying geometry along the contact hole depth optimizes both manufacturing ease and structural integrity.
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of: providing a material layer having a contact pad therein; forming a dielectric layer on the material layer and the contact pad; forming a doped oxide layer on the dielectric layer; forming an oxide layer on the doped oxide layer; performing a first etching process to remove part of the oxide layer, part of the doped oxide layer, and part of the dielectric layer to form a first contact hole; performing a second etching process to remove part of the doped oxide layer to form a second contact hole; and forming a conductive layer in the second contact hole to form a contact plug.