DRAM Storage Node Contact Structure With PVD Tungsten Layers
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Solution Overview
Problem
The challenge in DRAM device manufacturing is the difficulty in fabricating more memory cells within a practical device size while maintaining sufficient capacitance and signal-to-noise ratio, as the cell area decreases, leading to reduced performance due to shorter refresh cycle times.
Innovation Solution
A storage node contact structure is developed with a substrate having a dielectric layer and recess, filled with a first tungsten metal layer, followed by a planarization step and a second tungsten metal layer formed using physical vapor deposition (PVD), dividing the conductive layer into upper and lower layers for improved surface smoothness and electrical conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the cell area is decreased to fit more memory cells on a DRAM device, then the device capacity increases, but the capacitance of the storage capacitor decreases leading to reduced signal-to-noise ratio and performance
Solution Approach 1:
The patent transitions from planar capacitor structures to vertically stacked capacitor structures, moving the storage capacitor into the third dimension. This allows the capacitor to be formed over the access FETs rather than requiring additional lateral space, thereby maintaining sufficient capacitance while enabling higher device capacity through increased cell density.
Solution Approach 2:
The storage capacitor is nested over the access FET structure, with the capacitor layers positioned above the transistor. This nested configuration allows the capacitor to utilize the vertical space above the FET, effectively combining the FET and capacitor into a compact stacked cell structure that maintains capacitance while reducing the lateral footprint.
2Productivity
If the cell area is decreased to increase memory cell density, then more cells fit on the device, but the refresh cycle time decreases resulting in reduced performance
Solution Approach 1:
By stacking the capacitor vertically over the FET, the patent maintains sufficient capacitance value despite reduced cell area. This preserved capacitance ensures that the charge storage capability remains adequate, thereby maintaining acceptable refresh cycle times even as cell density increases.
3Ease of manufacture
If a single-layer conductive structure is used for the storage node contact, then the manufacturing process is simpler, but the electrical conductivity and surface smoothness are insufficient
Solution Approach 1:
The conductive layer of the storage node contact is divided into multiple segments or layers. This segmented structure allows each layer to be optimized for specific functions: lower layers provide structural foundation and adhesion, while upper layers provide superior electrical conductivity and surface smoothness. The multi-layer approach maintains manufacturing feasibility while significantly improving electrical performance.
Solution Approach 2:
The patent employs a composite conductive structure with multiple layers of different materials or treatments. This composite approach combines the advantages of different materials to achieve both good adhesion to the underlying structure and excellent electrical conductivity at the contact interface, thereby improving reliability without overly complicating the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the quality of the memory device by reducing resistance and improving electrical conductivity, thereby increasing the memory device's performance and capacity without increasing the overall device size.
Implementation Method 1
a second tungsten metal layer is formed on the first tungsten metal layer by a physical vapor deposition (PVD) method
Data Source
AI summary
The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).