DRAM Controller Low Priority Command Management
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Solution Overview
Problem
Memory subsystems face inefficiencies in managing memory commands, particularly in prioritizing requests to ensure high priority requests are processed promptly while avoiding overrepresentation of low priority requests in the DRAM controller, leading to suboptimal performance and quality of service.
Innovation Solution
The memory subsystem dynamically adjusts the maximum number of low priority memory requests that can be outstanding in the DRAM controller based on the number of high priority commands in the cache controller command queue, setting it to a high value when few high priority requests are present and a low value when many high priority requests are pending, ensuring high priority requests are prioritized.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the maximum number of low priority memory requests in the DRAM controller is increased to maximize utilization, then the DRAM controller utilization is improved, but the processing efficiency of high priority requests deteriorates
Solution Approach 1:
The patent implements dynamic adjustment of the maximum number of outstanding low priority commands based on the number of high priority commands in the queue. When high priority commands exceed a threshold, the limit on low priority commands is reduced to ensure prompt processing of high priority requests. When high priority commands are few, the limit is increased to maximize DRAM controller utilization. This dynamic parameter adjustment resolves the contradiction between utilization and response time.
Solution Approach 2:
The patent changes the parameter of maximum outstanding low priority commands from a fixed value to a variable that adapts based on system conditions (number of high priority commands). This parameter change allows the system to optimize between two conflicting objectives: maximizing utilization when possible, and ensuring low latency for high priority requests when necessary.
2Speed
If the maximum number of low priority memory requests in the DRAM controller is decreased to prioritize high priority requests, then the high priority request processing efficiency is improved, but the DRAM controller utilization deteriorates
Solution Approach 1:
The system dynamically adjusts the limit on low priority commands based on real-time conditions. When high priority commands are present in significant numbers, the limit is lowered to prioritize their processing. When high priority commands are scarce, the limit is raised to maintain high utilization. This prevents the DRAM controller from being underutilized when high priority requests are not competing for resources.
Solution Approach 2:
The parameter controlling the number of low priority commands is changed from static to adaptive, allowing the system to optimize performance characteristics based on workload composition. This resolves the contradiction by adjusting the parameter to favor speed when high priority requests dominate, and favor utilization when they do not.
3Device complexity
If a fixed maximum number of low priority commands is set in the DRAM controller, then the device complexity is reduced, but the system adaptability and quality of service deteriorate
Solution Approach 1:
The system performs self-adjustment by automatically modifying the maximum number of low priority commands based on its own internal state (number of high priority commands in the queue). This self-service mechanism provides adaptability without requiring complex external control systems, maintaining relatively simple device architecture while achieving high quality of service through autonomous parameter adjustment.
Data Source
AI summary
A method is described for managing issuance of memory commands. The method includes determining whether a number of high priority commands from a cache controller meets a first threshold. In response to meeting the first threshold, a second threshold, which indicates a maximum number of low priority commands allowed in a low latency memory command queue, is set to a first value. In response to not meeting the first threshold, the second threshold is set to a second value. The method further selects a memory command for issuance from the cache controller command queue, wherein the memory command is a high priority memory command when the number of low priority memory commands stored in the low latency memory controller command queue meets the second threshold and is a low priority memory command when the number of low priority memory commands does not meet the second threshold.