DRAM Counting Circuit With Decoded Threshold Module Selection
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Solution Overview
Problem
Existing Error Counters (ECs) in DRAMs have complex circuit designs with many connecting wires and logic devices, leading to large circuit areas and high implementation complexity.
Innovation Solution
A counting circuit with a first decoding module and first counting module, which includes multiple cascaded counting sub-modules, adaptively selects a target counting module based on decoded mode signals to output counting pulse signals at integer multiples of predefined thresholds, reducing circuit complexity and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional Error Counter (EC) is used in DRAM, then error counting function is achieved, but circuit area increases and complexity increases due to many connecting wires and logic devices
Solution Approach 1:
The counting circuit is divided into multiple counting modules (first counting module, second counting module, third counting module) that can be independently selected and activated. Each module handles specific counting tasks, allowing the system to break down the complex error counting function into manageable segments rather than using a single large complex counter.
Solution Approach 2:
The decoding module receives mode signals and generates decoded signals that can select different counting modules based on operational requirements. This multi-functional approach allows the same circuit structure to serve multiple counting purposes (error counting, frame counting, superframe counting) by activating different modules, reducing the need for separate dedicated circuits for each function.
2Reliability
If traditional Error Counter (EC) is used in DRAM, then error counting function is achieved, but circuit area increases due to many connecting wires and logic devices
Solution Approach 1:
The counting circuit is divided into multiple counting modules (first counting module, second counting module, third counting module) that can be independently selected and activated. Each module handles specific counting tasks, allowing the system to break down the complex error counting function into manageable segments rather than using a single large complex counter.
Solution Approach 2:
Multiple counting functions (error counting, frame counting, superframe counting) are merged into a unified counting circuit structure that shares common components such as the decoding module and mode signal input. By combining these functions in a single integrated circuit rather than using separate counters, the overall circuit area is reduced while maintaining all necessary counting capabilities.
3Adaptability or versatility
If multiple counting modules are used to reduce circuit complexity, then adaptability improves, but device complexity increases
Solution Approach 1:
The decoding module serves as an intermediary between the mode signal input and the multiple counting modules. It receives the mode signal, decodes it according to preset rules, and generates the appropriate decoded signal to activate the correct counting module. This intermediary approach simplifies the selection process by providing a systematic decoding mechanism rather than requiring complex direct control logic.
Solution Approach 2:
The decoding module is pre-configured with preset decoding rules that determine which counting module should be activated based on the mode signal. This preliminary setup of decoding logic allows the system to automatically and quickly select the appropriate counting module without requiring complex real-time decision-making circuitry, thereby reducing operational complexity.
Data Source
AI summary
A counting circuit, a semiconductor memory, and a counting method are provided. The counting circuit includes a first decoding module and a first counting module, and the first decoding module is connected with the first counting module. The first decoding module is configured to receive a first mode signal, and decode the first mode signal to generate a decoded signal; and the first counting module includes at least one counting sub-module, and is configured to: determine, according to the decoded signal, a selected target counting module from the at least one counting sub-module, receive the counting signal, count the counting signal through the target counting module, and output a first counting pulse signal every time when a counting value corresponding to the counting signals reaches an integer multiple of a counting threshold.