DRAM CRC and On-Die ECC for Link and Cell Error Isolation
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Solution Overview
Problem
The increasing bit errors and decreasing yield in dynamic random access memories (DRAMs) due to shrinking fabrication design rules pose challenges in ensuring reliable data transmission and storage.
Innovation Solution
Incorporation of a cyclic redundancy check (CRC) engine and an on-die error correction code (ECC) engine in semiconductor memory devices to detect and correct errors in data transmission and memory cells, utilizing CRC generators and checkers to generate error flags and perform ECC encoding and decoding operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fabrication design rules are shrunk to increase memory capacity, then storage density is improved, but bit error rate increases and yield decreases
Solution Approach 1:
The patent applies preliminary action by performing CRC error detection on incoming data before it is written to memory cells. The CRC engine calculates checksums and compares them against expected values, identifying errors in advance before they are stored, thereby preventing propagation of erroneous data while maintaining high-density storage capabilities
Solution Approach 2:
The patent introduces CRC engine and error detection circuits as intermediary components between the memory controller and memory cell array. These intermediaries intercept data transmissions, perform error detection through checksum calculations, and filter out erroneous data before it reaches the vulnerable high-density memory cells, thus resolving the reliability issue without sacrificing storage capacity
2Quantity of substance
If fabrication design rules are shrunk to increase memory capacity, then storage density is improved, but manufacturing yield decreases
Solution Approach 1:
The patent implements self-service through on-die error detection capabilities built into the memory device itself. The CRC engine automatically detects and flags errors in data being written to or read from memory, enabling the device to self-diagnose and self-correct issues without requiring external testing or rework, thereby improving manufacturing yield while maintaining high capacity
Solution Approach 2:
The patent employs feedback mechanisms where error detection results from CRC operations are fed back to the memory controller and system parity check logic. This feedback loop enables real-time identification of manufacturing defects and transmission errors, allowing for corrective actions that improve overall manufacturing yield while preserving the benefits of shrunk design rules
3Reliability
If CRC engine and ECC engine are added to detect and correct errors, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the CRC error detection engine and ECC error correction engine into a unified error handling architecture within the memory device. By combining these functions and sharing common resources such as parity check logic and data paths, the patent achieves comprehensive error detection and correction capabilities while minimizing the increase in device complexity through functional integration rather than separate independent circuits
Data Source
AI summary
A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.