DRAM CRC Engine for Separating Link and Memory Errors
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Solution Overview
Problem
Dynamic random access memories (DRAMs) face increasing bit errors and yield decreases due to shrinking fabrication design rules, necessitating effective error detection and correction mechanisms during data transmission and within memory cells.
Innovation Solution
Incorporation of a cyclic redundancy check (CRC) engine and on-die error correction code (ECC) engine in semiconductor memory devices to detect and correct errors in both data transmission and memory cells, utilizing system parity data to generate error flags and perform encoding and decoding operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fabrication design rules are shrunk to increase memory density, then memory capacity is improved, but bit errors increase and yield decreases
Solution Approach 1:
The patent applies preliminary action by performing CRC error detection on incoming data before it is written to memory cells. The CRC engine calculates checksums and compares them against stored parity data to identify errors proactively, preventing corrupted data from being committed to the memory array. This advance detection mechanism addresses the increasing bit error rates caused by fabrication shrinkage.
Solution Approach 2:
The patent introduces an intermediary CRC error detection system between the data transmission channel and the memory storage system. This intermediary layer includes CRC engines that calculate and verify checksums, acting as a mediator to filter out errors before they reach the memory cells. The system uses parity data as an intermediate reference to detect transmission errors independently of storage errors.
2Reliability
If CRC error detection is added to detect transmission errors, then error detection capability is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the CRC engine to perform multiple functions: it detects transmission errors in incoming data, verifies data integrity before storage, and works alongside the existing ECC system. The same CRC infrastructure serves both error detection and data validation purposes, reducing the need for separate dedicated circuits and minimizing overall device complexity increase.
Solution Approach 2:
The patent implements self-service by having the memory system generate and store its own parity data during write operations, which is then automatically used by the CRC engine for error detection during read operations. The system serves itself by maintaining internal consistency checks without requiring external validation hardware, reducing the complexity burden on the overall device architecture.
3Measurement precision
If system parity data is stored in memory cells for error detection, then error detection accuracy is improved, but memory resource utilization decreases
Solution Approach 1:
The patent applies local quality by storing parity data in specific dedicated locations within the memory array rather than uniformly distributing all data types. The system selectively allocates certain memory cells to hold parity information for CRC calculations, allowing high-precision error detection in critical areas while maintaining normal data storage efficiency in other regions. This localized approach optimizes both detection accuracy and overall resource utilization.
Data Source
AI summary
A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.