DRAM CRC Control for Unused 8-Bit Data Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current DRAM devices and memory systems face challenges in effectively managing and controlling unused 8-bit data, leading to inefficiencies and potential errors in data transmission and storage.
Innovation Solution
The proposed solution involves a DRAM device with a control signal generator, CRC unit, row decoder, column decoder, and memory cell array that performs CRC operations on both upper and lower data groups, generating error signals based on the second CRC result signal regardless of the first, allowing for efficient storage and transmission of data while disabling internal functions related to unused data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CRC operations are performed on both upper and lower data groups, then data integrity is improved, but power consumption increases due to unnecessary operations on unused data
Solution Approach 1:
The patent implements dynamic control of the CRC unit by generating a control signal that enables or disables CRC operations on the upper data group based on whether the upper data terminals are actually used. This dynamic switching allows the system to perform CRC operations only when necessary, resolving the contradiction between maintaining data integrity through continuous CRC operations and reducing power consumption by avoiding unnecessary operations on unused data.
2Use of energy by moving object
If internal function blocks are controlled based on usage status, then power consumption is reduced, but device complexity increases due to additional control logic
Solution Approach 1:
The control signal generator is designed to serve multiple functions: it detects whether the upper data terminals are used, generates the appropriate control signal to enable or disable CRC operations, and coordinates the overall data transmission control. By making this single component multi-functional, the patent reduces power consumption through intelligent control without significantly increasing device complexity.
Data Source
AI summary
A DRAM device includes first terminals, second terminals, third terminals, a control signal generator, a CRC unit, a row decoder, a column decoder, and a memory cell array. The control signal generator generates a control signal. The CRC unit performs a first CRC logical operation on a first data group including qn-bit first data generated by inputting n-bit first data q times, generates a first CRC result signal, performs a second CRC logical operation on a second data group including qn-bit second data by inputting n-bit second q times, generates a second CRC result signal, and generates an error signal based on the first CRC result signal and the second CRC result signal. The error signal is generated based on the second CRC result signal regardless of the first CRC result signal in response to the control signal.