DRAM CRC Control for Unused Data Terminals
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Solution Overview
Problem
Current DRAM devices and memory systems face challenges in effectively managing and controlling unused 8-bit data, leading to inefficiencies and potential errors in data transmission and storage.
Innovation Solution
The proposed solution involves a DRAM device with a control signal generator, CRC unit, row decoder, column decoder, and memory cell array that perform CRC operations on input data groups, generating error signals based on CRC results, and disabling internal functions related to unused data terminals to reduce power consumption and prevent erroneous signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CRC operations are performed on all data groups including unused 8-bit data, then data transmission completeness is improved, but power consumption increases and erroneous error signals may be generated
Solution Approach 1:
The patent extracts and identifies unused data groups (e.g., unused 8-bit data in x2n DRAM devices) from the data transmission stream. The control signal generator detects which data groups are actually used versus unused, allowing the system to perform CRC operations only on the necessary data groups, thereby avoiding unnecessary power consumption while maintaining data transmission reliability.
Solution Approach 2:
The patent implements dynamic control of CRC operations based on real-time detection of data usage status. The control signal generator dynamically generates control signals that enable or disable CRC operations for specific data groups depending on whether they are being used. This dynamic approach allows the system to adapt power consumption to actual operational needs rather than continuously performing CRC on all data groups.
2Reliability
If internal function blocks process unused data, then data handling completeness is improved, but error signal accuracy deteriorates
Solution Approach 1:
The patent extracts unused data groups from the processing pipeline by detecting their status through the control signal generator. Once identified, these unused data groups are excluded from CRC operations and error signal generation. This extraction prevents erroneous error signals from being generated based on unused data while ensuring that only valid used data groups contribute to error detection accuracy.
Solution Approach 2:
The patent implements a feedback mechanism where the control signal generator monitors data usage status and generates control signals that feed back to the CRC unit and error signal generator. This feedback loop ensures that the system continuously adapts its processing behavior based on actual data usage, preventing erroneous error signals while maintaining comprehensive handling of all used data groups.
3Use of energy by moving object
If control mechanisms are added to manage unused data, then power consumption efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements a control signal generator that performs multiple functions: detecting unused data groups, generating control signals to enable/disable CRC operations, and coordinating with the error signal generator. This multi-functional component achieves power consumption efficiency without requiring separate dedicated circuits for each function, thereby limiting the increase in device complexity while still managing unused data effectively.
4Reliability
If CRC operations are continuously performed on all data terminals, then data validation completeness is improved, but system efficiency deteriorates
Solution Approach 1:
The patent applies partial action by performing CRC operations only on the subset of data groups that are actually used, rather than continuously performing CRC on all data terminals. The control signal generator identifies which data groups require validation and enables CRC operations only for those groups. This partial approach maintains data validation completeness for all used data while avoiding the excessive action of validating unused data, thereby improving system efficiency.
Data Source
AI summary
A DRAM device includes first terminals, second terminals, third terminals, a control signal generator, a CRC unit, a row decoder, a column decoder, and a memory cell array. The control signal generator generates a control signal. The CRC unit performs a first CRC logical operation on a first data group including qn-bit first data generated by inputting n-bit first data q times, generates a first CRC result signal, performs a second CRC logical operation on a second data group including qn-bit second data by inputting n-bit second q times, generates a second CRC result signal, and generates an error signal based on the first CRC result signal and the second CRC result signal. The error signal is generated based on the second CRC result signal regardless of the first CRC result signal in response to the control signal.