DRAM Write Circuit With Selective DBI Flipping for Lower Bus Power
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) faces challenges in reducing power consumption while maintaining signal integrity and data reliability, particularly due to excessive flipping of the global bus during write operations, which increases current consumption.
Innovation Solution
A write operation circuit for semiconductor memory that includes a serial-to-parallel conversion circuit, a data buffer module with NMOS transistors, a DBI decoding module, and a precharge module, which performs data flipping and decoding to minimize global bus flips, thereby reducing power consumption by ensuring more data bits are '1' during write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the global bus is flipped during write operations to accommodate more '0' data bits, then data representation flexibility is improved, but current consumption increases due to excessive bus flips
Solution Approach 1:
The patent inverts the traditional DBI approach by performing serial-to-parallel conversion first, then selectively flipping only specific parallel data bits that require inversion, rather than flipping the entire global bus. This inversion of the processing sequence dramatically reduces unnecessary bus flips and associated current consumption while maintaining data representation flexibility.
Solution Approach 2:
The patent segments the global bus data into multiple parallel data streams through serial-to-parallel conversion, allowing independent processing and selective flipping of individual data bits or small groups. This segmentation enables precise control over which data bits are flipped, minimizing the number of bus flips required and reducing overall current consumption.
2Loss of energy
If serial-to-parallel conversion is performed on DBI data before flipping, then the number of global bus flips is reduced, but circuit complexity increases
Solution Approach 1:
The patent performs serial-to-parallel conversion as a preliminary action before the DBI flipping operation. By converting the serial DBI data to parallel form first, the system can efficiently determine which specific data bits require flipping and execute only those necessary flips, thereby reducing overall power consumption despite the added conversion circuitry.
Solution Approach 2:
The serial-to-parallel conversion circuit acts as an intermediary between the serial DBI input and the parallel data buffer, enabling intelligent selection of which data bits to flip. This intermediary component facilitates the transition from a high-power bus-wide flip approach to a low-power selective bit-flip approach, justifying its added complexity through significant power savings.
3Use of energy by moving object
If more data bits are ensured to be '1' during write operations, then power consumption is reduced, but data buffering complexity increases
Solution Approach 1:
The patent introduces dynamic control over data buffering through the DBI decoding module, which selectively flips data bits based on the converted DBI information. This dynamic approach allows the system to adaptively ensure more '1' bits in the buffered data, reducing power consumption during write operations while managing buffering complexity through intelligent, conditional processing.
Data Source
AI summary
Embodiments provide one write operation circuit, which includes: a serial-to-parallel conversion circuit that performs serial-to-parallel conversion on a first DBI data of a DBI port to generate a second DBI data for transfer by a DBI signal line, and that generates an input data of a data buffer module depending on the second DBI data; a data buffer module that determines whether to flip a global bus depending on the input data of the data buffer module; the DBI decoding module that decodes a global bus data according to the second DBI data, and writes the decoded data into a memory bank, where decoding includes determining whether to flip the global bus data; and a precharge module that is coupled to a precharge signal line and that sets the initial state of the global bus to high.