DRAM Array Layout With Deep Trench Isolation For Crosstalk Reduction
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Solution Overview
Problem
As DRAM arrays are packed to higher densities, crosstalk between adjacent wordlines, known as row-hammer, becomes increasingly problematic, necessitating new architectures that alleviate or prevent this issue to enhance integration and packing density.
Innovation Solution
The proposed solution involves a DRAM array layout with wordlines and bitlines that are substantially orthogonal, where each cell active material structure has a unique connection to a bitline not shared with adjacent structures, and deep trenches filled with electrically insulative material to prevent crosstalk, unlike conventional DRAM configurations that share bitline connections and use electrically biased conductive materials for isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM arrays are packed to higher density, then integration and packing density are improved, but crosstalk between adjacent wordlines becomes increasingly problematic
Solution Approach 1:
The patent segments the semiconductor structure by introducing deep trenches that divide the array into isolated regions. These trenches physically separate adjacent wordlines and memory cells, preventing crosstalk while maintaining high density. Each trench acts as an independent isolation barrier, allowing dense packing without compromising electrical isolation.
Solution Approach 2:
The patent introduces deep trenches filled with electrically insulative material as an intermediary structure between adjacent wordlines. This insulative material acts as a mediator that blocks electrical interference and crosstalk while allowing the wordlines to remain in close proximity for high-density integration.
2Device complexity
If conventional DRAM configurations share bitline connections between adjacent structures, then device complexity is reduced, but crosstalk between adjacent wordlines increases
Solution Approach 1:
The patent segments the bitline connections by assigning unique bitline connections to each cell active material structure. This segmentation eliminates shared connections that could propagate crosstalk, while the deep trenches provide additional physical isolation to prevent interference between adjacent structures.
Solution Approach 2:
The patent extracts the problematic shared connection architecture and replaces it with unique dedicated connections for each cell. By removing the sharing aspect of bitline connections, the design eliminates a primary pathway for crosstalk propagation while maintaining electrical isolation through deep trenches.
3Ease of manufacture
If electrically biased conductive materials are used for isolation, then manufacturing is simplified, but crosstalk prevention becomes insufficient at high densities
Solution Approach 1:
The patent changes the electrical parameter of the isolation material from conductive to electrically insulative. This parameter change transforms the isolation mechanism from electrical biasing to physical insulation, providing superior crosstalk prevention at high densities while remaining compatible with standard semiconductor manufacturing processes.
Solution Approach 2:
The patent transitions from two-dimensional planar isolation to three-dimensional deep trench isolation. By extending the isolation structure vertically into deep trenches, the design provides enhanced electrical isolation that effectively blocks crosstalk paths without complicating the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This architecture effectively reduces crosstalk between adjacent wordlines, allowing for higher integration and packing density without shared source/drain regions between transistors, thereby improving the electrical isolation and performance of DRAM arrays.
Implementation Method 1
deep trenches filled with electrically insulative material to prevent crosstalk
Data Source
AI summary
Some embodiments include a DRAM array layout. Wordlines extend along a first direction, and bitlines extend along a second direction that crosses the first direction. Cell active material structures are at intersections of the wordlines and bitlines. The cell active material structures have a first side coupled to a bitline and a second side coupled to a capacitor. The second side is on an opposite side of a wordline passing through a cell active material structure relative to the first side. Each cell active material structure has a connection to a bitline which is not shared with any other cell active material structures. Some embodiments include DRAM arrays and semiconductor constructions.