DRAM Delay Control Circuit With PVT-Calibrated Constant Delay Steps
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Dynamic Random Access Memories (DRAMs) face challenges in accurately transmitting signals to command/address pins due to decreasing data bit times and varying process-voltage-temperature (PVT) characteristics, which affect the delay of command/address signals, especially as DRAMs become faster.
Innovation Solution
A delay control circuit is implemented with bias inverters, RC circuits, and a ZQ calibrator to adjust impedance and compensate for PVT characteristics, ensuring a constant delay step independent of operating frequency, using step and trim codes to control the delay cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DRAM speed is increased to reduce data bit time, then productivity is improved, but signal transmission accuracy to command/address pins deteriorates due to PVT variations
Solution Approach 1:
The patent changes the delay parameters of the delay cell dynamically based on PVT conditions. The delay control circuit adjusts the delay amount by controlling the switching timing of transmission gates, which changes the effective resistance and capacitance values in the delay path. This allows the delay cell to maintain accurate constant-step delay characteristics across different process, voltage, and temperature conditions, thereby ensuring signal transmission accuracy at high DRAM speeds.
2Stability of the object's composition
If a delay cell with constant step delay is used to train DRAM, then signal synchronization is improved, but delay accuracy deteriorates due to PVT characteristics variations
Solution Approach 1:
The patent implements a feedback mechanism where the delay control circuit continuously monitors the PVT conditions and adjusts the delay cell parameters accordingly. The control circuit receives information about process variations, voltage levels, and temperature, then modifies the delay amount through controlled switching of transmission gates. This feedback-based adjustment ensures that the delay cell maintains accurate constant-step delay characteristics, resolving the contradiction between signal synchronization stability and delay accuracy under PVT variations.
3Manufacturing precision
If the number of RC circuits is increased to achieve finer delay steps, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent employs dynamic control of the delay cell using transmission gates that can be selectively switched on and off based on the desired delay amount. Instead of using a fixed large number of RC circuits, the control circuit dynamically activates only the necessary number of RC circuits or adjusts their effective values through the switching action. This dynamic approach achieves fine delay step precision while avoiding the complexity of having all RC circuits permanently connected, as only a subset is actively used at any given time.
Data Source
AI summary
A delay control circuit includes: a delay cell including a plurality of bias inverters, first RC circuits, and second RC circuits, the delay cell activates a number of first RC circuits in response to a step code, delays a signal by a delay time based on the number of the activated first RC circuits, and outputs the delayed signal; a ZQ calibrator including pull-up and pull-down circuits, the ZQ calibrator adjusts a number of activated pull-up and pull-down circuits, and inputs a pull-up and pull-down voltage, based on a calibration code to the bias inverters; and a step adjuster including a first ring oscillator including test delay cells, the step adjuster determining characteristics of the first and second RC circuits and activates a number of second RC circuits based on the characteristics and an operating frequency of the delay control circuit.