DRAM Delay Control Circuit for Constant RC Delay Steps
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) systems face challenges in maintaining a constant delay step for signal input to command/address pins, especially as operating frequencies vary and process-voltage-temperature (PVT) characteristics change.
Innovation Solution
A delay control circuit is implemented, comprising a delay cell with bias inverters and RC circuits, a ZQ calibrator for impedance adjustment, and a step adjuster that determines the activation of RC circuits based on an operating frequency and PVT characteristics, ensuring a constant delay step independent of these factors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay cell with fixed RC circuits is used to delay command/address signals, then the delay step is constant under ideal conditions, but the delay step varies when PVT (process-voltage-temperature) characteristics change or operating frequency varies
Solution Approach 1:
The patent applies dynamics by making the RC circuit configuration adjustable rather than fixed. The delay cell dynamically reconfigures the number of activated RC circuits based on operating conditions (frequency and PVT characteristics). This allows the delay step to remain constant across varying conditions by adapting the circuit configuration in real-time, resolving the contradiction between delay consistency and environmental adaptability.
Solution Approach 2:
The patent changes physical parameters (number of activated RC circuits) based on operating conditions. By monitoring frequency and PVT characteristics, the system adjusts which RC circuits are activated to maintain a constant delay step. This parameter adjustment mechanism resolves the contradiction by allowing the delay cell to adapt its physical configuration to maintain reliability under varying conditions.
2Measurement precision
If the number of RC circuits is increased to provide finer delay adjustment, then delay precision improves, but circuit complexity and power consumption increase
Solution Approach 1:
The patent segments the delay adjustment function into multiple independent RC circuits that can be individually activated. Each RC circuit provides a discrete delay step, and by selectively activating specific segments (RC circuits), the system achieves fine-grained delay control. This segmentation approach provides precise delay adjustment without requiring all circuits to be active simultaneously, managing complexity through modular design.
Solution Approach 2:
The patent applies partial action by activating only the necessary number of RC circuits required for the desired delay step, rather than activating all available circuits. The system determines the minimum required delay and activates only that many RC circuits, providing sufficient precision while minimizing power consumption and effective circuit complexity. This resolves the contradiction by providing exact rather than excessive delay capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively compensates for PVT variations and operating frequency changes, ensuring that signals are input to DRAM command/address pins in a constant and accurate manner, thereby improving the reliability and efficiency of DRAM systems.
Implementation Method 1
a delay cell including a plurality of bias inverters, a plurality of first RC circuits, and a plurality of second RC circuits, wherein the delay cell activates a number of first RC circuits in response to a value of a step code, delays a signal that was externally input, by a delay time based on the number of the activated first RC circuits
Implementation Method 2
a ZQ calibrator including a plurality of pull-up circuits and a plurality of pull-down circuits, wherein the ZQ calibrator adjusts a number of activated pull-up circuits and a number of activated pull-down circuits, to adjust an impedance of a transmission line
Implementation Method 3
a step adjuster including a first ring oscillator including a plurality of test delay cells having a circuit structure, equal to a circuit structure of the delay cell, wherein the step adjuster determines characteristics of the first and second RC circuits, based on a pulse period that depends on whether or not the second RC circuits included in the first ring oscillator are activated
Data Source
AI summary
A delay control circuit includes: a delay cell including a plurality of bias inverters, first RC circuits, and second RC circuits, the delay cell activates a number of first RC circuits in response to a step code, delays a signal by a delay time based on the number of the activated first RC circuits, and outputs the delayed signal; a ZQ calibrator including pull-up and pull-down circuits, the ZQ calibrator adjusts a number of activated pull-up and pull-down circuits, and inputs a pull-up and pull-down voltage, based on a calibration code to the bias inverters; and a step adjuster including a first ring oscillator including test delay cells, the step adjuster determining characteristics of the first and second RC circuits and activates a number of second RC circuits based on the characteristics and an operating frequency of the delay control circuit.