Stacked DRAM Die Partitioning for Cost-Efficient 3D Memory
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Solution Overview
Problem
Conventional stacked DRAM devices use substantially identical memory dies, which limits cost savings and viability as standalone memory devices, as features needed on one die may not be necessary on others, leading to inefficiencies in memory capacity and cost-effectiveness.
Innovation Solution
The implementation of a stacked memory device configuration using a master and slave memory die, where the slave die has a memory interface circuit decoupled from low-resistance metal layers, and interconnects with the master die via through-silicon-vias (TSVs), allowing for differential feature distribution and standalone die fabrication, reducing unnecessary metal layers and enhancing cost efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If substantially identical memory dies are used in stacked configuration, then manufacturing consistency is improved, but cost efficiency and feature optimization deteriorate
Solution Approach 1:
The patent segments the memory stack into master dies and slave dies with different functional configurations. Master dies contain complete memory arrays and interfaces, while slave dies contain only memory arrays. This segmentation allows each die type to be optimized independently for its specific function, improving cost efficiency by eliminating unnecessary features on slave dies while maintaining manufacturing consistency through standardized fabrication processes for each die type.
Solution Approach 2:
The patent applies local quality by giving different structural characteristics to different positions in the stack. Master dies at specific positions include interface circuits and control logic, while slave dies at other positions have simplified structures without these components. This allows features to be present only where needed, reducing unnecessary manufacturing complexity and cost on slave dies while maintaining overall system consistency.
2Adaptability or versatility
If features are included on all memory dies, then standalone die viability is improved, but memory capacity and density deteriorate
Solution Approach 1:
The patent merges the functionality of multiple dies by interconnecting master dies and slave dies through TSVs to form a unified memory stack. The slave dies, while incapable of standalone operation, contribute their memory array capacity to the master dies, effectively increasing total memory capacity. This merging allows the system to achieve high capacity while using simplified slave die structures.
Solution Approach 2:
The patent transitions from two-dimensional planar memory organization to three-dimensional stacked architecture. By stacking multiple dies vertically and interconnecting them through TSVs, the system achieves higher total capacity in a smaller footprint. Slave dies contribute to capacity in this third dimension without requiring standalone functionality, resolving the contradiction between capacity and adaptability.
3Ease of manufacture
If unnecessary metal layers are retained on slave dies, then manufacturing simplicity is improved, but production cost and device complexity deteriorate
Solution Approach 1:
The patent extracts unnecessary metal layers and interface circuits from slave dies, retaining only the essential memory array structures. This extraction reduces the complexity of slave dies while maintaining their memory storage function. The removed features are only present on master dies where they are needed for control and interface operations.
Solution Approach 2:
The patent applies partial action by implementing metal layers and interface circuits only on the extent necessary for each die type. Slave dies receive only the minimal structure needed for memory storage, while master dies receive the full complement of layers and circuits. This partial implementation reduces overall device complexity and manufacturing cost without compromising functionality.
Data Source
AI summary
A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.