Stacked DRAM Die Partitioning Using TSV-Linked Master and Slave Chips
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Solution Overview
Problem
Conventional stacked DRAM devices use substantially identical memory dies, which limits cost-saving opportunities and makes them less viable as stand-alone memory devices due to unnecessary features being fabricated on all dies.
Innovation Solution
The use of master and slave memory dies with distinct features, where the slave die has a memory interface circuit decoupled from low-resistance metal layers and communicates with the master die through TSVs, allowing for cost-effective fabrication and increased flexibility in memory module design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If substantially identical memory dies are used in stacked DRAM devices, then manufacturing consistency and reliability are improved, but cost-saving opportunities are lost and adaptability deteriorates
Solution Approach 1:
The patent applies local quality by differentiating features between master and slave memory dies. Slave dies have a decoupled memory interface circuit separated from low-resistance metal layers, while master dies have fully connected interface circuits. This allows each die type to have optimized features for its specific role in the stack, improving overall adaptability while maintaining reliability through standardized interconnection methods.
Solution Approach 2:
The invention segments the memory interface circuit functionality between master and slave dies. Slave dies contain only the memory core with decoupled interface circuits, while master dies contain both memory core and fully functional interface circuits. This segmentation enables cost-effective fabrication by allowing slave dies to be manufactured with fewer features, while still achieving full functionality when stacked with master dies.
2Ease of manufacture
If features are fabricated on all memory dies, then stand-alone device viability is improved, but manufacturing cost increases
Solution Approach 1:
The patent implements local quality by providing different feature sets on master and slave dies. Slave dies are manufactured with decoupled interface circuits that do not connect to low-resistance metal layers, reducing material usage and process complexity. Master dies are manufactured with complete features including connected interface circuits. This differentiation allows cost-effective manufacturing while maintaining stand-alone viability for master dies.
Solution Approach 2:
The invention extracts the fully connected interface circuit features from slave dies, leaving only the memory core functionality. This extraction reduces the quantity of materials and process steps required for slave die manufacturing, lowering costs. The removed features are provided on master dies, which can function as stand-alone devices if needed.
3Reliability
If memory interface circuit is coupled to low-resistance metal layers on slave die, then signal integrity is improved, but cost-effectiveness and density deteriorate
Solution Approach 1:
The patent applies local quality by differentiating the coupling arrangement between master and slave dies. Slave dies have decoupled interface circuits separated from low-resistance metal layers, while master dies have coupled interface circuits connected to low-resistance metal layers. This local differentiation optimizes signal integrity where needed (master dies) while improving cost-effectiveness and density (slave dies without the coupling structure).
Solution Approach 2:
The invention resolves the signal integrity concern by moving the fully coupled interface circuit functionality to the master die in a different position within the stack. The slave die's decoupled interface communicates with the master die's coupled interface through TSVs, effectively providing signal integrity at the system level rather than requiring it at each individual slave die level.
Data Source
AI summary
A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.