DRAM Memory Gate Dielectric Uniformity With SiGe Epitaxy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As DRAM sizes reduce, the introduction of High-K Metal Gate (HKMG) to address SiO2 leakage issues leads to challenges in maintaining consistent device performance due to varying oxidation rates between N-type and P-type active regions, affecting the thickness of gate dielectric layers.
Innovation Solution
Forming an epitaxial layer on the P-type active region and ensuring the thickness of the gate dielectric layers on both the N-type and P-type regions are substantially the same by using a method that includes forming a silicon germanium epitaxial layer and adjusting gas flow rates to stabilize the interface lattice, thereby maintaining consistent thickness across both regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If SiO2 is used as dielectric in power transistor, then device structure is simple, but leakage problem occurs as DRAM size reduces
Solution Approach 1:
The patent changes the dielectric material parameter from SiO2 to SiGe epitaxial layer, altering the material composition to achieve lower leakage current while maintaining device functionality as DRAM scales down
Solution Approach 2:
The patent uses a composite structure combining SiGe epitaxial layer with gate dielectric layer, creating a high-K metal gate (HKMG) configuration that addresses leakage issues while managing device complexity
2Object-generated harmful factors
If HKMG is introduced to solve leakage problem, then leakage current is reduced, but device performance consistency deteriorates due to varying oxidation rates
Solution Approach 1:
The patent applies different materials and structures to different regions: SiGe epitaxial layer is formed on P-type active region while N-type active region maintains original structure, creating locally optimized zones that address oxidation rate variations
Solution Approach 2:
The SiGe epitaxial layer is formed in advance on the P-type active region before gate dielectric deposition, pre-stabilizing the interface lattice structure to ensure uniform oxidation rates and consistent gate dielectric thickness across different transistor types
3Ease of manufacture
If gate dielectric layer thickness varies between N-type and P-type regions, then manufacturing process is simpler, but device performance uniformity deteriorates
Solution Approach 1:
The SiGe epitaxial layer is formed preliminarily on the P-type active region to create a stable interface lattice structure before gate dielectric deposition, ensuring that subsequent oxidation produces uniform thickness across both N-type and P-type regions
Solution Approach 2:
The patent modifies the interface lattice structure by introducing SiGe epitaxial layer, changing the physical and chemical parameters of the P-type region surface to match oxidation characteristics of the N-type region, thereby achieving uniform gate dielectric thickness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes device performance by ensuring uniform gate dielectric layer thickness, reducing leakage current and enhancing the overall stability and efficiency of the memory.
Implementation Method 1
forming a silicon germanium epitaxial layer and adjusting gas flow rates to stabilize the interface lattice
Data Source
AI summary
A memory and a method for preparing a memory are provided. The method for preparing the memory includes: providing a substrate, in which the substrate includes a first N-type active region and a first P-type active region; forming an epitaxial layer covering the first P-type active region, in which the epitaxial layer exposes the first N-type active region; simultaneously forming a first gate dielectric layer covering the first N-type active region and a second gate dielectric layer covering the epitaxial layer, in which a thickness of the first gate dielectric layer is substantially the same as a thickness of the second gate dielectric layer; forming a first gate covering the first gate dielectric layer to form a first N-channel Metal Oxide Semiconductor (NMOS) device; and forming a second gate covering the second gate dielectric layer to form a first P-channel Metal Oxide Semiconductor (PMOS) device.