DRAM DLL Control Circuit for Single-Step Delay Setting
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Solution Overview
Problem
Dynamic random access memory (DRAM) experiences issues with jitter, leading to overflow or underflow during the delay operation of the delay locked loop (DLL) circuit, which affects synchronization and data integrity.
Innovation Solution
A control circuit with a temporary delay amount selection unit generates multiple temporary delay signals, selecting the one closest to the input clock signal phase, allowing for a single setting of the delay amount without multiple adjustments, thereby suppressing jitter and overflow/underflow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the delay amount is gradually changed multiple times to achieve synchronization, then the DLL circuit can achieve proper delay amount, but the impact of jitter increases causing overflow or underflow
Solution Approach 1:
The patent applies preliminary action by generating multiple temporary delay signals in advance with different delay amounts before the actual delay operation. The temporary delay amount selection unit pre-calculates and prepares all possible delay options, then selects the most appropriate one based on phase comparison with the input clock signal. This eliminates the need for multiple gradual adjustments during operation, thereby suppressing jitter impact and preventing overflow or underflow while achieving precise delay amount.
2Manufacturing precision
If multiple delay operations are performed to set the delay amount, then the proper delay can be achieved, but the occurrence of overflow or underflow increases
Solution Approach 1:
The patent applies segmentation by dividing the delay operation into two distinct phases: a temporary delay amount selection phase and a final delay execution phase. The temporary delay amount selection unit segments the delay setting process by generating multiple temporary delay signals with different delay amounts, selecting the appropriate one through phase comparison, and then using this selected delay amount for the actual delay operation. This segmentation allows precise delay setting in one operation rather than multiple adjustments, reducing overflow or underflow while maintaining accuracy.
3Measurement precision
If the delay amount is adjusted gradually, then synchronization can be achieved, but the number of delay operations increases
Solution Approach 1:
The patent applies preliminary action by performing the delay amount selection in advance through the temporary delay amount selection unit. This unit generates multiple temporary delay signals with different delay amounts, compares their phases with the input clock signal, and selects the most appropriate delay amount before the actual delay operation. This preliminary selection eliminates the need for multiple gradual adjustments during operation, achieving precise phase synchronization in a single delay operation and thereby improving productivity while maintaining accuracy.
Data Source
AI summary
The control circuit of this invention includes: a control unit, configured to generate a control signal indicating a delay amount; a delay line unit, configured to receive an input clock signal, and based on the control signal, perform a delay operation to generate an output clock signal; and a temporary delay amount selection unit configured to receive the output clock signal, generates a plurality of temporary delay signals that delay the output clock signal by a respective plurality of different temporary delay amounts, then performs a selection operation to select whichever of the temporary delay signals is closest in phase to the input clock signal, and outputs an output signal that indicates the temporary delay amount of the selected temporary delay signal. The control unit sets the delay amount according to the output signal indicating the temporary delay amount.