DRAM DLL Clock Pulse Gating for Idle Power Reduction
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Solution Overview
Problem
Dynamic random access memory (DRAM) chips in computer systems face high power consumption due to the need to maintain delay-locked loops (DLLs) active even in idle modes, leading to increased latency and energy wastage.
Innovation Solution
A memory device with a circuit that selects and applies a subset of internal clock pulses to the DLL during idle mode, using a clock gating circuit called the CAclk pulse swallower to reduce the activity of the DLL, thereby minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the DLL is kept on during idle mode to avoid re-locking latency, then the turn-on time is improved, but power consumption increases
Solution Approach 1:
The patent applies periodic action by switching the DLL between active and idle modes based on memory access patterns. During idle periods, the DLL is turned off to save power, and during active periods, it is enabled to provide fast operation. This periodic switching resolves the contradiction by accepting brief re-locking latency in exchange for significant power savings during extended idle periods.
Solution Approach 2:
The patent implements dynamics by making the DLL state (on/off) variable rather than fixed. The system dynamically transitions the DLL between operational and standby states based on real-time detection of memory access activity. This dynamic behavior allows the system to optimize the trade-off between turn-on time and power consumption by adapting to actual workload conditions.
2Use of energy by moving object
If the DLL is turned off during idle mode to save power, then power consumption is reduced, but re-locking latency increases
Solution Approach 1:
The patent uses periodic action by implementing scheduled DLL activation. Instead of keeping the DLL continuously on, the system periodically activates it based on predicted or detected memory access patterns. This approach reduces power consumption during genuine idle periods while minimizing the impact of re-locking latency by activating the DLL just before or during expected access operations.
Solution Approach 2:
The patent applies preliminary action by pre-loading or pre-warming the DLL before actual memory operations begin. The system detects upcoming memory access patterns and activates the DLL in advance, allowing it to be fully locked and ready before data operations start. This eliminates or reduces re-locking latency during actual operations while maintaining power savings during true idle periods.
3Reliability
If the DLL operates at full frequency continuously, then operational readiness is maintained, but power consumption increases
Solution Approach 1:
The patent implements dynamics by adjusting the DLL operating frequency based on actual memory access demands. Instead of running continuously at full frequency, the system dynamically scales the DLL frequency - using full frequency during intensive operations and reducing or stopping operation during idle periods. This dynamic frequency adjustment maintains operational readiness when needed while significantly reducing power consumption during low-demand periods.
Solution Approach 2:
The patent applies parameter changes by modifying the DLL's operational parameters (frequency, enable/disable state) based on system conditions. The controller monitors memory access patterns and adjusts the DLL's frequency and operational state accordingly. This parameter adaptation allows the system to maintain full operational readiness at high frequency during intensive workloads while reducing power consumption by lowering frequency or disabling the DLL during lighter workloads.
Data Source
AI summary
Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.