DRAM DLL Pulse Swallowing for Low-Power Idle Clocks
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Solution Overview
Problem
Dynamic random access memory (DRAM) chips in computer systems face high power consumption due to the need to maintain delay-locked loops (DLLs) in idle mode, as turning them off results in significant turn-on latency, leading to inefficiencies in power management.
Innovation Solution
A clock gating circuit, referred to as the command and address clock (CAclk) pulse swallower, is used to select and modify clock pulses, applying a reduced activity clock to the DLL during idle mode, thereby reducing power consumption while ensuring the DLL remains operational for instant activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the DLL is turned off during idle mode to save power, then power consumption is reduced, but the turn-on time increases significantly due to re-locking requirements
Solution Approach 1:
The patent applies periodic action by gating the clock signal to the DLL at reduced frequency during idle mode. Instead of completely turning off the DLL, the clock is periodically enabled at lower activity levels, allowing the DLL to maintain its locked state with minimal power consumption while being ready for immediate full-speed operation when needed.
Solution Approach 2:
The patent implements dynamics by dynamically adjusting the clock gating behavior based on the operational state of the memory device. During idle mode, the clock gating circuit reduces clock pulse frequency to minimize power consumption, while upon detecting an active mode transition, it immediately restores full clock frequency to ensure rapid DLL reactivation without re-locking delays.
2Speed
If the DLL is kept on during idle mode to avoid turn-on latency, then activation speed is maintained, but power consumption increases
Solution Approach 1:
The clock gating circuit employs periodic action by selectively enabling clock pulses to the DLL at reduced frequency during idle periods. This periodic clocking maintains the DLL's operational readiness and phase relationships while significantly reducing the energy consumption associated with continuous full-frequency clocking, thus resolving the contradiction between speed and power consumption.
Solution Approach 2:
The patent applies parameter changes by modifying the clock frequency parameter fed to the DLL based on operational mode. During idle mode, the clock frequency is reduced through gating, lowering power consumption while maintaining the DLL's ability to quickly resume full operation. The system dynamically changes the clock parameter from full frequency to reduced frequency and back, optimizing both speed and power characteristics.
Data Source
AI summary
Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.