DRAM DLL Control for Read-Phase Skew and Access Time
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Solution Overview
Problem
In high-speed DRAM technologies, a skew between the calibrated clock and the reference clock can occur due to voltage level drops in the clock tree during READ operations, leading to increased access time, which existing solutions like widening the clock tree power bus or adding capacitors cannot effectively address without increasing the DRAM area.
Innovation Solution
A control circuit and method for the DRAM that increases the number of DLL updates based on phase difference detection by a phase detector, activating the DLL every clock cycle when a READ command is received, ensuring the skew is eliminated before output data is sent, thereby shortening access time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the filter activates the DLL to update the delay line only when phase difference is detected continuously (4 times), then jitter in output data is prevented, but skew between calibrated clock and reference clock increases during READ operation, leading to longer access time
Solution Approach 1:
The filter dynamically changes its activation threshold based on the operation mode. During READ operations, the filter is configured to activate the DLL with a lower threshold (single phase difference detection), while during normal operations, it requires continuous detection (4 times). This dynamic adaptation allows the system to optimize between stability and speed based on operational context.
Solution Approach 2:
The invention changes the parameter of filter activation threshold based on the command type. When a READ command is detected, the filter parameter is adjusted to activate the DLL update mechanism with single phase difference detection, whereas other operations maintain the original 4-time continuous detection requirement. This parameter change enables the system to reduce access time for READ operations while maintaining stability for other operations.
2Reliability
If the clock tree power bus width is increased or large capacitors are added to the clock tree power bus, then voltage level drop during READ operation is reduced, but DRAM area increases
Solution Approach 1:
The invention replaces the physical hardware solution (wider power bus or larger capacitors) with a control logic solution. Instead of modifying the physical clock tree structure to prevent voltage drop, the system uses the filter and phase detector to dynamically control DLL updates, achieving clock signal stability through software/firmware control rather than hardware expansion.
Solution Approach 2:
The invention changes the operational parameters of the DLL during READ operations by adjusting the filter activation threshold. This parameter change allows the DLL to update the delay line more frequently during READ operations, compensating for voltage level drops without requiring physical modifications to the power bus or capacitor sizes.
Data Source
AI summary
A dynamic random access memory (DRAM) includes a delay lock loop (DLL), a clock tree, an off-chip driver (OCD), a phase detector (PD) and a filter. The DLL receives a reference clock and updates a delay line, and then outputs a calibrated clock via the clock tree; the PD receives the calibrated clock via the clock tree and detects a phase difference between the calibrated clock and the reference clock; and the filter activates the DLL to update the delay line according the phase difference, wherein when a READ command is received, the filter increases the number of activations for the DLL to update the delay line, thereby shortening the access time of the DRAM.