DRAM DLL Refresh Control for Voltage-Induced Access Time Shift
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Solution Overview
Problem
Conventional DRAM circuits face access time shift issues due to voltage drops, which are typically addressed by elongating power buses or increasing capacitors, but these solutions become impractical as working frequency increases and chip size decreases.
Innovation Solution
A detecting circuit with a delay-locked loop module, clock tree module, and voltage-detecting module that adjusts the refresh frequency based on voltage comparisons, allowing for timely phase adjustments of the clock signal without requiring elongated power buses or increased capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power buses are elongated or capacitors are increased to solve access time shift problems, then voltage stability is improved, but chip size increases and working frequency capability decreases
Solution Approach 1:
The patent changes the operating parameters of the delay-locked loop module by dynamically adjusting its refresh frequency based on detected voltage levels. When voltage drops are detected, the refresh frequency is increased to maintain timing relationships, thereby addressing access time shift problems through parameter adjustment rather than physical structure modification.
Solution Approach 2:
The patent implements a feedback mechanism where the voltage-detecting module continuously monitors voltage levels and provides information to the control module, which then adjusts the refresh frequency of the delay-locked loop module accordingly. This closed-loop feedback system maintains voltage stability and timing relationships without requiring additional physical components.
2Reliability
If power buses are elongated or capacitors are increased to solve access time shift problems, then voltage stability is improved, but working frequency capability worsens
Solution Approach 1:
The patent makes the delay-locked loop module dynamic by enabling it to adjust its refresh frequency in real-time based on voltage conditions. This dynamic adaptation allows the system to maintain stable timing relationships at higher working frequencies without requiring additional capacitors or elongated power buses that would limit frequency capability.
3Reliability
If refresh frequency is increased to compensate for voltage drops, then timing relationship is maintained, but power consumption increases
Solution Approach 1:
The patent uses periodic voltage detection and conditional refresh frequency adjustment, where the system monitors voltage levels and only increases refresh frequency when voltage drops are detected. This periodic monitoring approach maintains timing relationships while avoiding continuous high-power operation, thereby reducing overall power consumption compared to constantly operating at maximum refresh frequency.
Data Source
AI summary
The present disclosure provides a detecting circuit. The detecting circuit includes a clock module, a clock receiver, a delay-locked loop module, a clock tree module, an off-chip driver, a pad, a phase detector, a voltage-detecting module and a control module. The clock module provides a clock signal to the clock receiver. The clock receiver sends the clock signal to the pad through the delay-locked loop module, the clock tree module and the off-chip driver. The control module is coupled to the voltage-detecting module and the delay-locked loop module. The voltage-detecting module is coupled between the control module and the clock tree module, and is configured to detect a voltage of the clock tree module and to send a voltage comparison information to the control module. The control module is configured to control a refresh frequency of the delay-locked loop module.