DRAM Delay-Locked Loop Using One Adjustable Delay Line

Solution Overview

Problem

In Dynamic Random Access Memory (DRAM), the existing delay-locked loops (DLLs) require multiple adjustable delay lines to synchronize and lock four-phase clock signals, leading to increased manufacturing costs and high power consumption.

Innovation Solution

The proposed DLL architecture reduces the number of adjustable delay lines by using a frequency division module, a first adjustable delay line, a delay module, and a latching module to generate a group of target clock signals with a preset phase difference, thereby reducing circuit area and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multiple adjustable delay lines are used to synchronize four-phase clock signals, then phase synchronization accuracy is improved, but circuit area and power consumption increase

Engineering Contradiction:

Improvephase synchronization accuracyVSAvoidcircuit area

Core Design Contradiction:

Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent segments the clock signal processing into two independent paths: a frequency division path that generates an intermediate clock signal, and a delay path that generates a sampling clock signal. This segmentation allows the system to use only one adjustable delay line instead of multiple delay lines, reducing circuit area while maintaining phase synchronization capability through the coordinated operation of these paths

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a frequency division module as an intermediary that converts the input clock signal into an intermediate clock signal with a different frequency. This intermediary component enables the system to achieve four-phase clock generation through a single adjustable delay line by combining the frequency-divided signal with the delayed sampling signal, thereby reducing the number of delay lines needed

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If multiple adjustable delay lines are used to synchronize four-phase clock signals, then phase synchronization capability is improved, but power consumption increases

Engineering Contradiction:

Improvephase synchronization capabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent segments the clock signal processing into two independent paths: a frequency division path that generates an intermediate clock signal, and a delay path that generates a sampling clock signal. This segmentation allows the system to use only one adjustable delay line instead of multiple delay lines, reducing circuit area while maintaining phase synchronization capability through the coordinated operation of these paths

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a frequency division module as an intermediary that converts the input clock signal into an intermediate clock signal with a different frequency. This intermediary component enables the system to achieve four-phase clock generation through a single adjustable delay line by combining the frequency-divided signal with the delayed sampling signal, thereby reducing the number of delay lines needed

Inventive Principle:

Principle #24Intermediary (Mediator)

3Manufacturing precision

If four main adjustable delay lines are designed to calibrate four phase clock signals, then clock signal calibration accuracy is improved, but manufacturing cost increases

Engineering Contradiction:

Improveclock signal calibration accuracyVSAvoidmanufacturing cost

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent segments the clock signal processing into two independent paths: a frequency division path that generates an intermediate clock signal, and a delay path that generates a sampling clock signal. This segmentation allows the system to use only one adjustable delay line instead of multiple delay lines, reducing circuit area while maintaining phase synchronization capability through the coordinated operation of these paths

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent uses a frequency division module to create a copy of the input clock signal at a different frequency (intermediate clock signal). This copied signal is then processed through a single adjustable delay line to generate the required phase relationships, eliminating the need for multiple identical delay lines and reducing manufacturing complexity and cost

Inventive Principle:

Principle #26Copying

Data Source

PatentUS12341515B2Delay-locked loop, delay locking method, clock synchronization circuit, and memory

Publication Date: 2025.06.24 CHANGXIN MEMORY TECH INC

AI summary

Provided are a delay-locked loop (DLL), a delay locking method, a clock synchronization circuit, and a memory. The DLL includes: a frequency division module, configured to receive an input clock signal, perform frequency division on the input clock signal, and output an intermediate clock signal; a first adjustable delay line, configured to receive the intermediate clock signal, adjust and transmit the intermediate clock signal, and output a synchronous clock signal; a delay module, configured to receive the input clock signal, perform delay transmission on the input clock signal, and output a sampling clock signal; and a latching module, configured to receive the sampling clock signal and the synchronous clock signal, latch the synchronous clock signal on the basis of the sampling clock signal, and output a group of target clock signals.