DRAM DQ Pin Power Reduction via Data Masking Control
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Solution Overview
Problem
Existing DRAM memory systems face challenges in reducing non-core power consumption, particularly in demanding bandwidth-intensive use cases, as existing solutions like reducing operating voltages or data activity factors are either ineffective or limited to specific types of data.
Innovation Solution
A system and method that utilize a data masking power reduction module within a System on Chip (SoC) to selectively control DQ pins, reducing memory I/O power by driving them to power-saving states during data masking operations, thereby minimizing data activity and static power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If operating voltages are reduced to decrease power consumption, then non-core power is reduced, but bandwidth-intensive performance deteriorates
Solution Approach 1:
The patent applies dynamic voltage scaling by selectively applying different voltages to different groups of I/O drivers based on real-time activity detection. The memory controller identifies which I/O drivers are actively transmitting data and applies full voltage only to those, while reducing voltage to inactive drivers, thereby dynamically optimizing the trade-off between power consumption and performance
Solution Approach 2:
The patent implements local quality by applying different voltage levels to different spatial locations (groups of I/O drivers) within the memory interface. Instead of uniformly reducing voltage across all I/O drivers, the system applies high voltage locally to active drivers and low voltage to inactive drivers, enabling selective power reduction without compromising overall bandwidth performance
2Loss of energy
If data activity factor is reduced to decrease power consumption, then non-core power is reduced, but effectiveness is limited to specific data types
Solution Approach 1:
The patent implements a universal power reduction mechanism that works across all data types and workloads. The activity detection and selective voltage scaling approach is workload-agnostic, automatically adapting to any pattern of memory access regardless of data type, making it universally applicable to both bandwidth-intensive and power-constrained scenarios
3Loss of energy
If frequency of operation is temporarily reduced to decrease power consumption, then non-core power is reduced, but bandwidth performance deteriorates
Solution Approach 1:
The patent dynamically adjusts the operating characteristics of individual I/O driver groups based on their activity state. By detecting which drivers are actively transmitting data and maintaining their full frequency and voltage, while putting inactive drivers into a low-power state, the system achieves power reduction without temporarily reducing the overall operating frequency and compromising bandwidth performance
Data Source
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AI summary
Systems and methods are disclosed for reducing memory I/O power. One embodiment is a system comprising a system on chip (SoC), a DRAM memory device, and a data masking power reduction module. The SoC comprises a memory controller. The DRAM memory device is coupled to the memory controller via a plurality of DQ pins. The data masking power reduction module comprises logic configured to drive the DQ pins to a power saving state during a data masking operation.