DRAM Word Line Driver Layout for Lower Bit Line Capacitance
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Solution Overview
Problem
The design of dynamic random access memory (DRAM) faces challenges in optimizing the layout of word line drivers and sense amplifiers, leading to increased size and coupling capacitance between bit lines, which affects read/write performance.
Innovation Solution
The layout of word line drivers is redesigned with transistors arranged in a channel width direction perpendicular to the word line direction, and the drivers are arranged in a specific pattern to reduce their size and coupling capacitance, using advanced fabrication processes for the semiconductor structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If word line drivers are arranged in conventional layout, then device functionality is achieved, but memory block size increases and coupling capacitance between bit lines increases
Solution Approach 1:
The patent applies dimensionality change by arranging transistors in the channel width direction (third direction) that is perpendicular to both the word line direction (first direction) and bit line direction (second direction). This three-dimensional spatial arrangement optimizes the layout by utilizing the channel width dimension, thereby reducing the footprint in the plane of the memory block while minimizing coupling capacitance between bit lines.
Solution Approach 2:
The patent employs asymmetric arrangement of word line drivers relative to memory blocks, where odd-numbered word line drivers are disposed on one side of the memory block and even-numbered word line drivers are disposed on the other side. This asymmetric configuration optimizes space utilization and reduces coupling capacitance by strategically positioning drivers to minimize interference with bit lines.
2Quantity of substance
If memory capacity is increased, then storage capability is improved, but device size increases
Solution Approach 1:
The patent utilizes the third dimension (channel width direction) for arranging transistors, which allows higher integration density without increasing the planar footprint. By orienting transistor channels perpendicular to the word line direction, the design efficiently packs more memory cells within the same memory block area, thereby increasing capacity without proportionally increasing device size.
Solution Approach 2:
The patent segments the memory array into multiple memory banks, with each bank containing multiple memory blocks. This segmentation allows for independent optimization of each block's layout and enables parallel operation, improving both capacity and efficiency while maintaining compact overall device dimensions.
Data Source
AI summary
The present application provides a memory, a forming method of the memory and a memory system. The memory includes a first semiconductor structure and a second semiconductor structure coupled with the first semiconductor structure. The first semiconductor structure includes a memory array, word lines and bit lines; wherein the memory array includes memory banks each including memory blocks; the word lines and bit lines are coupled with the memory blocks, a length direction of the word lines is a first direction, a length direction of the bit lines is a second direction perpendicular to the first direction. The second semiconductor structure includes word line drivers corresponding to each memory block respectively, the word line drivers being coupled with the word lines; the word line driver includes transistors arranged in a channel width direction of the transistor. The channel width direction of the transistor is perpendicular to the first direction.