DRAM Driving Circuit Layout for Signal Matching in Compact Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing layout and routing designs for power supply driving circuits in Dynamic Random Access Memory (DRAM) do not fully consider various factors, resulting in a large area, reduced signal matching, and consistency.
Innovation Solution
A layout for a driving circuit that includes P-type transistors, N-type transistors, and four test modules, arranged in an upper-lower symmetrical structure, which improves signal matching and consistency while reducing external influences and saving area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If existing layout and routing designs are used for power supply driving circuits, then the circuit can be implemented, but the area occupied is large and signal matching and consistency are reduced
Solution Approach 1:
The patent applies asymmetry by intentionally introducing dummy transistors to create an asymmetric layout that balances the electrical characteristics. The dummy transistors are added to compensate for the asymmetric routing paths from power supply nodes to the driving transistors, thereby achieving symmetry in electrical performance rather than physical layout, which resolves the contradiction between compact area and signal matching consistency.
Solution Approach 2:
The patent changes the electrical parameters by adding dummy transistors with specific width and length parameters to match the parasitic capacitance and resistance of the routing paths. By adjusting the parameters of dummy transistors (such as width-to-length ratio), the layout achieves balanced signal characteristics, improving signal matching and consistency while maintaining a compact area.
2Shape
If existing layout and routing designs are used for power supply driving circuits, then the circuit can be implemented, but the layout lacks symmetrical structure and compact arrangement
Solution Approach 1:
The patent uses asymmetry as a means to achieve symmetry in electrical characteristics. By adding dummy transistors to compensate for asymmetric routing, the final electrical layout achieves symmetry in performance metrics (signal matching, parasitic balance) while the physical structure remains practically implementable, thus achieving symmetrical structure without excessive design complexity.
Solution Approach 2:
The dummy transistors serve dual purposes: they act as electrical compensations for signal matching and simultaneously serve as placeholders that simplify the overall layout design. The self-service principle is applied where the dummy transistors automatically balance the electrical characteristics without requiring complex external adjustments, thereby achieving symmetrical structure with manageable design complexity.
3Object-affected harmful factors
If existing layout and routing designs are used for power supply driving circuits, then the circuit can be implemented, but external factors have greater influence on signal quality
Solution Approach 1:
The patent applies preliminary anti-action by proactively adding dummy transistors during the layout phase to counteract the harmful effects of asymmetric routing and external interference. This preemptive compensation balances the electrical characteristics before the circuit operates, reducing the influence of external factors on signal quality and improving manufacturing precision in signal matching.
Solution Approach 2:
By adjusting the parameters of dummy transistors (width, length, position), the patent optimizes the electrical characteristics to minimize the impact of external factors. The parameter changes in dummy transistor design allow precise control over parasitic effects, thereby improving signal matching precision and reducing susceptibility to external interference.
Data Source
AI summary
A layout of a driving circuit, a semiconductor structure and a semiconductor memory are provided. The layout includes P-type transistors, N-type transistors and four test modules. The four test modules are distributed on both sides of the P-type transistors and the N-type transistors in an upper-lower symmetrical structure, and the P-type transistors and the N-type transistors have an upper-lower structure distribution in the middle of the four test modules.