DRAM Drowsy Mode Exit Command Hazard Prevention
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Solution Overview
Problem
During the transition from drowsy mode to active mode in DRAM devices, external inputs can be unstable, leading to potential command hazards such as incorrect execution of commands like the mode register set (MRS) command, which may result in data corruption or overwrite, especially during manufacturing tests.
Innovation Solution
A control signal is used to prevent external inputs from initiating commands during the exit from drowsy mode, and a clock enable control module ensures that commands are not issued until the system is fully powered and stable, utilizing logic gates to selectively disable specific external inputs and the clock signal to prevent faulty command execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the memory device continuously refreshes during idle periods (self-refresh mode), then power consumption is reduced by alternating power-on and power-off phases, but external inputs become unstable during the power-off phase which can lead to command decoding errors and data corruption
Solution Approach 1:
The patent applies preliminary action by detecting the power phase state before external inputs are processed. A detection circuit monitors whether the memory device is in power-on or power-off phase, and based on this detection, controls the command decoder to ignore or block external inputs received during the power-off phase. This prevents unstable inputs from causing command decoding errors while maintaining the power-saving benefits of self-refresh mode.
2Productivity
If voltage generators power on during exit from drowsy mode to allow command execution, then the system can respond to external commands, but the generators take time to reach full power causing external inputs to be unstable during the power recovery period
Solution Approach 1:
The patent introduces an intermediary control mechanism between the unstable external inputs and the command decoder during the power recovery period. A control circuit monitors the power phase state and actively manages the command decoder's responsiveness to external inputs. During the power recovery period when inputs are unstable, the control circuit prevents these inputs from being decoded, thereby protecting the system from command errors while still allowing rapid response once power stabilization is confirmed.
3Loss of time
If the command decoder processes external inputs during power-off phase, then the system can potentially execute commands faster, but the decoded commands may be erroneous leading to data overwrite or corruption
Solution Approach 1:
The patent applies preliminary anti-action by proactively preventing harmful command decoding before it can occur. The detection circuit identifies when the memory device is in the power-off phase, and the control circuit subsequently blocks or ignores external inputs during this period. This preliminary protective action eliminates the risk of decoding erroneous commands while maintaining minimal delay, as the system is designed to quickly transition to power-on phase and resume normal operation.
Data Source
AI summary
A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode.