DRAM Spacer Structure With Dual Air Gaps for Dense Memory Cells
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Solution Overview
Problem
The challenge in semiconductor memory devices is to increase memory cell density while reducing leakage current and improving fabrication efficiency and reliability, particularly in DRAMs with recessed gate structures, where the complexity of processes and designs is heightened by the need for high integration and high density.
Innovation Solution
The formation of two air gap layers between bit lines and storage node contacts using storage node pads as a mask to remove material layers, simplifying the process and improving the delay between resistor and capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased to meet high integration requirements, then storage capacity is improved, but fabrication process complexity and design difficulty increase
Solution Approach 1:
The spacer structure is divided into multiple segments including first and second air gap layers, first and second spacers, and optional third air gap layers. This segmented approach allows each layer to be optimized independently for specific functions such as electrical isolation and mechanical support, enabling higher memory cell density while maintaining manageable fabrication complexity through modular construction
Solution Approach 2:
The invention transitions from planar gate structures to recessed gate structures with multi-layer spacer systems extending in vertical dimensions. The spacers are formed at different heights and positions (sidewalls of bit lines, sidewalls of plugs) creating a three-dimensional architecture that increases storage capacity without proportionally increasing planar fabrication complexity
2Reliability
If recessed gate structures are used to reduce leakage current, then reliability is improved, but fabrication complexity increases
Solution Approach 1:
Material layers including air gap layers and spacers are formed preliminarily on the sidewalls of bit lines and plugs before final capacitor structure fabrication. This preliminary formation of isolation structures ensures that leakage current paths are blocked early in the process, and subsequent fabrication steps can proceed with established geometric constraints that simplify later processing
Solution Approach 2:
The spacer structure acts as an intermediary element between the recessed gate structures and the capacitor structures. These spacers provide both electrical isolation to prevent leakage and geometric definition to guide subsequent fabrication steps, mediating between the complex recessed gate architecture and the capacitor formation processes
Data Source
AI summary
The present disclosure relates to a semiconductor memory device and a fabricating method thereof, and the semiconductor memory device includes a substrate, bit lines, plugs and a spacer structure. The bit lines are separately disposed on the substrate, and the plugs are also disposed on the substrate to alternately arrange with the bit lines. The spacer structure is disposed on the substrate, between each of the bit lines and each of the plugs. The spacer structure includes a first air gap layer, a first spacer and a second air gap layer, and the first air gap layer, the first spacer and the second air gap layer are sequentially stacked between sidewalls of the bit lines and the plugs. Therefore, two air gap layers may be formed between the bit lines and the storage node contacts to improve the delay between the resistor and the capacitor.