DRAM Dual Level Word Lines for Scaling
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Solution Overview
Problem
As semiconductor devices scale down, the dimensions for forming deep trench capacitors and strap structures shrink, posing challenges in maintaining effective electrical connections and capacitance in dynamic random access memory (DRAM) cells.
Innovation Solution
A semiconductor structure is developed with trench capacitors embedded in a substrate, featuring an inner electrode, node dielectric, outer electrode, and a conductive strap structure contacting the inner electrode, along with an access transistor and passing gate lines formed across two levels to ensure electrical connections and high capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dimensions of semiconductor devices are scaled down, then device density and integration are improved, but maintaining effective electrical connections and capacitance becomes difficult
Solution Approach 1:
The patent transitions from planar capacitors to three-dimensional deep trench capacitors, utilizing the vertical dimension to achieve higher capacitance density. The trench capacitor structure extends vertically into the substrate, providing increased surface area for charge storage without occupying additional lateral space, thus maintaining electrical connection effectiveness while scaling down device dimensions.
Solution Approach 2:
The patent employs nested conductive structures where the conductive strap structure is positioned within and overlying the trench capacitor structure. This nested arrangement allows multiple functional elements to occupy overlapping spatial regions, enabling effective electrical connections between the inner electrode and source region while maintaining compact device dimensions.
2Productivity
If dimensions of semiconductor devices are scaled down, then device density is improved, but capacitance maintenance becomes challenging
Solution Approach 1:
The deep trench capacitor structure utilizes the vertical dimension by etching trenches into the substrate and filling them with conductive materials. This three-dimensional configuration provides significantly increased surface area for charge storage compared to planar capacitors, enabling high capacitance values in a compact footprint that supports device scaling.
Solution Approach 2:
The patent employs composite material structures in the trench capacitor, utilizing different dielectric materials (first and second node dielectrics) with different etch selectivities. This allows for selective etching processes and optimized capacitor performance, achieving high capacitance while maintaining compatibility with scaled device dimensions.
3Device complexity
If deep trench capacitors and strap structures are formed with smaller dimensions, then device integration is improved, but electrical connection effectiveness deteriorates
Solution Approach 1:
The conductive strap structure is positioned within the trench capacitor structure, with the strap laterally contacting the inner electrode. This nested configuration allows the strap to be formed in the same lateral footprint as the capacitor, achieving effective electrical connection without requiring additional lateral space, thus supporting high device integration.
Solution Approach 2:
The patent utilizes the vertical dimension by forming the conductive strap structure that overlies the inner electrode and extends upward. This vertical arrangement provides effective electrical connection between the capacitor and source region while maintaining compact lateral dimensions, enabling high device integration.
Data Source
AI summary
A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer. Gate electrodes are formed as discrete structures that are not interconnected. After formation and planarization of a contact-level dielectric layer, passing gate lines are formed above the contact-level dielectric layer in a line level to provide electrical connections to the gate electrodes. Gate electrodes and passing gate lines that are electrically connected among one another constitute a gate line that is present across two levels.