DRAM Memory Structure With Dummy Bit Line Acid Barrier
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Solution Overview
Problem
Existing dynamic random access memory (DRAM) manufacturing methods face challenges in scaling down devices and ensuring reliability, particularly in preventing acid liquids from penetrating into the memory array region during the formation of capacitors, which requires additional masking steps and affects process yield and cost.
Innovation Solution
A method involving the formation of bit line structures, contacts, and a protective structure with a hard mask spacer at the boundary between the memory array and peripheral circuit regions, where the protective structure's top surface is higher than the bit line structures, using a hard mask spacer and etching processes to create an acid-resistant feature without an additional mask, thereby preventing acid penetration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an additional mask is designed to form a protective ring structure between the memory array region and the peripheral circuit region, then acid liquid penetration into the memory array region is prevented, but device complexity and manufacturing cost increase
Solution Approach 1:
The bit line structure itself serves as the protective barrier by extending into the peripheral circuit region and forming a physical barrier that prevents acid liquid penetration, eliminating the need for separate protective ring structures
Solution Approach 2:
The bit line structure performs dual functions: serving as an electrical conductor for memory operations and simultaneously acting as a protective barrier against acid liquid penetration during capacitor formation, thereby eliminating the need for dedicated protective structures
2Reliability
If an additional mask is designed to form a protective ring structure, then acid liquid penetration is prevented, but manufacturing time and process steps increase
Solution Approach 1:
The protective function is merged with the bit line structure formation process, where the bit line structure is extended into the peripheral circuit region to simultaneously serve as both the electrical conductor and the protective barrier, eliminating separate masking steps
3Area of moving object
If device scaling down is pursued to improve memory density, then storage capacity increases, but reliability and acid liquid penetration resistance decrease
Solution Approach 1:
The bit line structure is extended locally into the peripheral circuit region specifically at the boundary area where acid liquid penetration risk exists, providing enhanced protective coverage without increasing overall device area, thus maintaining memory density while improving reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of the memory structure by preventing acid liquids from entering the memory array region, improves process yield, and reduces production costs by eliminating the need for additional masking steps.
Implementation Method 1
depositing a protective layer on the substrate
Implementation Method 2
depositing a hard mask layer on the protective layer
Implementation Method 3
etching the protective layer with the hard mask spacer as an etching mask
Data Source
AI summary
A memory structure includes: a substrate including a memory array region and a peripheral circuit region; a plurality of bit line structures disposed in the memory array region of the substrate; a dummy bit line structure disposed on the substrate, wherein the dummy bit line structure is disposed in the memory array region and immediately adjacent to the peripheral circuit region; a plurality of contacts disposed between the bit line structures and in the memory array region; a dielectric layer disposed on the substrate and in the peripheral circuit region; and a protective structure disposed in the memory array region and immediately adjacent to the peripheral circuit region, wherein the protective structure includes the dummy bit line structure and a top surface of the protective structure is higher than top surfaces of the bit line structures.