DRAM Data Port Duty Cycle Output for Accurate Clock Calibration
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Solution Overview
Problem
In the semiconductor field, particularly in DRAM systems, there is a challenge in accurately adjusting the duty cycle of internal data clock signals to ensure proper data transmission and avoid distortion of the gating clock signal, which can lead to incorrect duty cycle adjustments.
Innovation Solution
The proposed solution involves an information transmission method where a memory receives a target command to output duty cycle data through specific data ports, which persists until a stop command is received, allowing for continuous sampling by the control apparatus without the need for a dedicated MRR command.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the memory uses a dedicated MRR command to output duty cycle data, then the control apparatus can obtain duty cycle information, but the interaction between control apparatus and memory increases, leading to higher power consumption and more complex command sequences
Solution Approach 1:
The patent combines the duty cycle data output function with the existing data port structure, allowing duty cycle data to be transmitted through the same data ports used for normal data operations. This merging eliminates the need for separate dedicated output mechanisms and reduces command interaction complexity while maintaining detection accuracy
Solution Approach 2:
The data ports are designed to serve multiple functions: they can output both normal data signals and duty cycle data signals. The memory can switch between different output modes based on command type, making the data ports universal interfaces that reduce overall system complexity without sacrificing measurement precision
2Ease of operation
If the duty cycle data is output continuously through data ports, then the control apparatus can sample data at any time, but the data port must maintain persistent signal output, increasing power consumption
Solution Approach 1:
Instead of continuous output, the patent implements periodic or on-demand duty cycle data output triggered by specific commands. The memory outputs duty cycle data only when a read command is issued, allowing the control apparatus to sample at convenient times without requiring persistent signal maintenance, thus reducing power consumption while preserving sampling flexibility
Solution Approach 2:
The memory autonomously manages the duty cycle data output timing and format, switching between normal data mode and duty cycle data mode based on received commands. This self-service approach allows the control apparatus to sample whenever needed without the memory requiring continuous power-intensive signal maintenance
3Productivity
If the gating clock signal is not properly adjusted, then the data transmission can proceed, but the duty cycle adjustment may be distorted, leading to incorrect adjustments
Solution Approach 1:
The patent performs duty cycle detection and adjustment before normal high-speed data transmission begins. By completing the duty cycle calibration in advance during initialization or setup phases, the system ensures accurate clock signaling for subsequent data transmission without compromising transmission speed or adjustment reliability
Data Source
AI summary
The present disclosure provides an information transmission method, a memory, a control apparatus. The method includes: receiving a first target command sent from the outside; and outputting first duty cycle data of an internal data clock signal through a first group of data ports based on the first target command, where the first duty cycle data persists at the first group of data ports at least until a first stop command sent from the outside is received.