Primitive-Polynomial ECC Engine for DRAM Bit Error Correction

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Solution Overview

Problem

The increasing bit errors and decreasing yield in DRAM devices due to reduced fabrication design rules affect the performance and reliability of semiconductor memory devices.

Innovation Solution

An ECC engine is integrated into the semiconductor memory device, utilizing a primitive polynomial-based ECC encoder and decoder to generate and correct errors in memory cells, including single, adjacent, and non-adjacent bit errors through different syndromes generated from a parity check matrix.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If fabrication design rules are reduced to increase memory density, then memory capacity is improved, but bit error rate increases

Engineering Contradiction:
Improvememory capacityVSAvoidbit error rate
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The ECC encoder performs preliminary error correction preparation by generating parity data before data is stored in the memory device. This allows the system to proactively prepare for potential bit errors that may occur during storage, rather than reacting to errors after they happen. The parity data is calculated in advance using the primitive polynomial-based ECC algorithm, enabling efficient error correction when read operations occur.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The ECC decoder implements a feedback mechanism by generating syndromes from read data and using these syndromes to identify and correct bit errors. The syndrome generation process provides feedback information about the state of the data, allowing the system to detect and correct errors automatically. This closed-loop feedback system continuously monitors and corrects bit errors, maintaining data integrity despite the increased error rate from reduced fabrication rules.

Inventive Principle:
Principle #23Feedback

2Reliability

If conventional ECC methods are used, then error correction is provided, but correction efficiency is insufficient for adjacent bit errors

Engineering Contradiction:
Improveerror correction capabilityVSAvoidcorrection efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies local quality by treating different types of bit errors with different correction approaches. Specifically, the system distinguishes between single bit errors and adjacent bit errors, and applies optimized correction methods for each case. The syndrome generation and analysis processes are tailored to efficiently handle adjacent bit errors, which are more complex to correct than single bit errors. This localized optimization of correction strategies improves overall correction efficiency while maintaining high reliability.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system changes parameters dynamically based on the type of error detected. The ECC decoder analyzes syndrome patterns to determine whether errors are single-bit or adjacent-bit errors, and adjusts the correction approach accordingly. This parameter-based differentiation allows the system to optimize correction efficiency for each error type, rather than using a uniform correction method that would be less efficient for adjacent bit errors.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If different correction methods are applied for single and adjacent bit errors, then correction accuracy is improved, but system complexity increases

Engineering Contradiction:
Improveerror detection accuracyVSAvoidECC decoder complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The ECC decoder is segmented into specialized sub-processes for handling different error types. The syndrome generation and analysis logic is divided into pathways that efficiently handle single bit errors versus adjacent bit errors. This segmentation allows each sub-process to be optimized for its specific error type, improving detection accuracy while keeping the overall complexity manageable through modular design. The primitive polynomial-based ECC framework provides a unified structure that accommodates these segmented correction methods.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12554576B2Error correction code engine of semiconductor memory device and semiconductor memory device
Publication Date: 2026.02.17 SAMSUNG ELECTRONICS CO LTD
  • US12554576B2 patent drawing
  • US12554576B2 patent drawing
  • US12554576B2 patent drawing

AI summary

An ECC engine of a semiconductor memory device includes an ECC encoder and an ECC decoder. The ECC encoder generates parity data based on main data based on a primitive polynomial and stores a codeword including the main data and the parity data in a target page. The ECC decoder reads the codeword from the target page based on an address to generate a syndrome and corrects at least one error bit in the read codeword based on the syndrome by respectively applying different syndromes to a single bit error in the read codeword, adjacent bit errors and non-adjacent bit errors occurring in non-adjacent two memory cells in the target page. The ECC decoder generates the different syndromes based on a parity check matrix generated as a function of the primitive polynomial. The primitive polynomial has an alpha matrix as a solution belonging to a Galois field.