Iterative DRAM ECC Decoding for Device Failure Correction
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Solution Overview
Problem
Existing ECC techniques for memory devices are costly in terms of parity bit requirements and fail to efficiently detect and correct errors due to single device failures or single row failures, leading to uncorrectable errors and silent data corruption.
Innovation Solution
The implementation of an iterative ECC decoding system that leverages knowledge of erasure locations to identify faulty DRAM components, reducing the search space and decoding delays, and using Reed-Solomon codes to correct more erasures than random errors, thereby addressing the limitations of conventional ECC schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chipkill ECC techniques are used to detect and correct entire device failures, then reliability is improved, but parity bit requirements increase significantly
Solution Approach 1:
The patent segments the error correction approach by distinguishing between different failure modes (access-corrupting failures vs. complete device failures) and applying different correction strategies. Instead of using comprehensive chipkill ECC for all scenarios, the system uses iterative decoding that targets specific failure patterns, reducing the need for excessive parity bits while maintaining reliability for the most common failure modes.
Solution Approach 2:
The patent changes the parameter of error correction by shifting from traditional ECC that corrects random bit errors to iterative decoding that handles erasures (known error locations). This parameter change allows the system to achieve better correction capability with fewer parity bits, as erasure correction is more efficient than general error correction.
2Quantity of substance
If conventional ECC techniques are used that cannot detect and correct entire device failures, then parity bit overhead is reduced, but uncorrectable errors increase
Solution Approach 1:
The patent introduces dynamics into the error correction process through iterative decoding. The system dynamically adapts its correction strategy by attempting to decode with different assumptions about which device caused the failure. This dynamic approach allows the system to handle access-corrupting failures effectively with reduced parity overhead, as the iterative process can identify and correct errors even when the initial decoding assumption is incorrect.
Solution Approach 2:
The iterative decoding mechanism incorporates feedback by using the results of each decoding attempt to inform subsequent attempts. When a decoding attempt fails, the system uses syndrome information and failure mode analysis to guide the next decoding attempt, creating a feedback loop that improves correction success rates without requiring additional parity bits.
3Reliability
If ECC techniques are designed to correct access-corrupting failures, then reliability for common failure modes is improved, but decoding complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-characterizing the failure modes (access-corrupting vs. complete device failures) and pre-computing syndromes that help identify the failure type. This preliminary analysis allows the iterative decoding process to start with informed assumptions, reducing the overall decoding complexity compared to attempting to correct all possible error patterns without prior classification.
Solution Approach 2:
The system applies local quality by tailoring the decoding strategy to the specific failure mode detected. Instead of using a uniform complex decoding approach for all errors, the system adapts its decoding complexity based on the local characteristics of the failure (e.g., which device is suspected, whether it's an access-corrupting or complete failure), optimizing the balance between reliability and complexity for each case.
Data Source
AI summary
Provided is a memory system comprising an error correction code (ECC) decoder configured to receive data from a memory. The ECC decoder includes a syndrome generator configured to calculate at least one of syndrome vector and an erasure value, the calculation being devoid of erasure location information and an error-location polynomial generator configured to determine error location and error/erasure value polynomials responsive to syndrome and erasure calculation values output from the syndrome generator. An error value generator confirms error values at one or more known error locations based upon the determined error/erasure value polynomials, and an error location generator search for an error evaluation value to confirm the known error locations based upon the determined error location polynomials. Outputs of the error value generator and the error location generator are combined to produce corrected data.