DRAM ECC Decoding With Iterative Erasure Marking
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Solution Overview
Problem
Existing ECC techniques for memory devices are costly in terms of parity bit requirements and fail to efficiently detect and correct errors due to single device failures or single row failures, leading to uncorrectable errors and silent data corruption.
Innovation Solution
The implementation of an iterative ECC decoding system that leverages knowledge of erasure locations to identify faulty DRAM components, reducing the search space and decoding delays, and using Reed-Solomon codes to correct more erasures than random errors, thereby addressing the limitations of conventional ECC schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC techniques are used to detect and correct errors, then reliability is improved, but parity bit requirements increase significantly
Solution Approach 1:
The patent segments the error correction approach by distinguishing between erasure errors (where location is known) and random errors (where location is unknown). This segmentation allows the system to apply different correction strategies: for erasures, only the value needs to be recovered rather than both location and value, thereby reducing the number of parity bits required while maintaining reliability
Solution Approach 2:
The patent changes the parameter of error location knowledge from unknown to known for erasure errors. By marking the locations of erasure errors, the system transforms the problem from correcting both location and value to only correcting values, which reduces the redundancy (parity bits) needed while preserving error correction capability
2Quantity of substance
If ECC techniques cannot detect and correct entire device failures, then parity bit requirements are reduced, but uncorrectable errors increase
Solution Approach 1:
The patent performs preliminary action by marking erasure locations before the actual error correction process. This preliminary marking of known error locations enables the decoder to focus computational resources on recovering only the erroneous values rather than searching for both locations and values, thereby improving the ability to correct device failures with fewer parity bits
Solution Approach 2:
The patent introduces an intermediary step of identifying and marking erasure locations between data retrieval and error correction. This intermediary process acts as a mediator that separates the error location identification from the error value correction, allowing the system to handle device failures more efficiently with reduced parity overhead
3Device complexity
If ECC techniques mark all bits from a single device as erasures, then decoding complexity is reduced, but false decoding errors may increase
Solution Approach 1:
The patent applies partial action by marking only the specific bits from a single device as erasures rather than all bits across multiple devices. This selective marking reduces decoding complexity by focusing on a limited set of potential errors while the verification step ensures false errors are caught and corrected, balancing complexity reduction with reliability maintenance
Data Source
AI summary
Provided is a memory system comprising a plurality of memory components; and a controller in communication with the plurality of memory components and configured to perform error correction code (ECC) decoding on a received word read from the plurality of memory components. The ECC decoding is configured to (i) detect one or more random errors in a portion of the received word, the portion corresponding to one of the components within the plurality, and (ii) correct the detected random errors; and when the correcting of the detected random errors fails, iteratively marking symbols in the remaining portions of the received word as erasures.