DRAM ECC Iterative Decoding for Single-Device Failure Recovery
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Solution Overview
Problem
Existing ECC techniques struggle to efficiently detect and correct errors due to memory device failures, particularly when an entire device fails or all bits in a read from a single device are corrupted, leading to uncorrectable errors and reduced reliability in memory systems.
Innovation Solution
The proposed ECC solution leverages the ability to correct more erasures than random errors by identifying a single faulty DRAM component based on successfully decoded components, reducing the search space for error location, and implementing an iterative decoding technique to correct errors efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC techniques are used to detect and correct errors, then reliability is improved, but device complexity increases due to additional parity bit requirements
Solution Approach 1:
The patent segments the error correction problem by dividing it into two distinct phases: a first decoding attempt using conventional ECC techniques for standard error correction, and a second decoding attempt using iterative decoding techniques specifically for uncorrectable errors. This segmentation allows each decoding method to be optimized for its specific purpose without requiring the full complexity of advanced techniques for all error scenarios.
Solution Approach 2:
The patent applies partial action by implementing iterative decoding only when the first decoding attempt fails to correct the error. Instead of applying complex iterative decoding to all error cases, the system uses it selectively for uncorrectable errors, thereby reducing overall computational complexity while maintaining high reliability for the most difficult error cases.
2Reliability
If iterative decoding technique is applied to correct uncorrectable errors, then reliability is improved, but decoding time increases
Solution Approach 1:
The patent implements periodic action through a two-stage decoding process where the first stage uses conventional ECC decoding for rapid error correction, and only if that fails does the system periodically attempt iterative decoding. This periodic application of the more time-consuming technique minimizes average decoding time while still providing correction for uncorrectable errors when they occur.
Solution Approach 2:
The patent applies preliminary action by performing conventional ECC decoding first to quickly handle the majority of correctable errors before attempting the more time-consuming iterative decoding. This preliminary filtering step reduces the average decoding time by resolving most errors in the faster first stage, reserving the slower iterative approach only for cases where it is truly needed.
3Reliability
If chipkill ECC techniques are used to achieve low AFR, then reliability is improved, but cost increases due to higher parity bit requirements
Solution Approach 1:
The patent segments the error correction capability into two layers: conventional ECC for standard protection and iterative decoding for enhanced protection against uncorrectable errors. This segmentation allows the system to achieve low AFR through the combined effect of both layers while using fewer total parity bits than pure chipkill approaches, as the iterative decoding recovers capability rather than relying entirely on additional redundancy bits.
Solution Approach 2:
The patent changes the operational parameters of the ECC system by dynamically switching between conventional decoding and iterative decoding modes based on error characteristics. This parameter change allows the system to adapt its correction capability to the actual error situation, achieving high reliability with optimized parity bit usage rather than requiring the fixed high overhead of chipkill for all scenarios.
Data Source
AI summary
Provided is a memory system comprising a plurality of memory components; and a controller in communication with the plurality of memory components and configured to perform error correction code (ECC) decoding on a received word read from the plurality of memory components. The ECC decoding is configured to (i) detect one or more random errors in a portion of the received word, the portion corresponding to one of the components within the plurality, and (ii) correct the detected random errors; and when the correcting of the detected random errors fails, iteratively marking symbols in the remaining portions of the received word as erasures.